[SYCL][FPGA] Add support for new attribute for loop pipelining #6254
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This patch adds support for new FPGA attribute called [[intel::fpga_pipeline(N)]] that takes a Boolean parameter.
N can be a template parameter or constexpr. If the user didn't provide a parameter, the default value of N would
be 1, which implies enable pipelining.
This attribute can be applied to loops.
Example syntax:
// will disable loop pipelining
[[intel::fpga_pipeline(0)]]
for (int i = 0; i<N; ++i) {...}
LLVM IR:
When applied on a loop, the LLVM IR should be attached to llvm.loop metadata:
!{!"llvm.loop.intel.pipelining.enable", i32 N}
The value of the !"llvm.loop.intel.pipelining.enable" metadata is an i32 value that corresponds to the boolean parameter N.
A value of 0 is used for not pipelining the loop.
A value of 1 is used for pipelining the loop.
If the parameter is not given, value of N will be the default value 1, which implies we will pipeline the loop, and the IR will look like
!{!"llvm.loop.intel.pipelining.enable", i32 1}
Error Message:
We should emit an error when [[intel::initiation_interval(k)]] and [[intel::fpga_pipeline(0)]] are used together:
"error: initiation_interval and fpga_pipeline(0) attributes are not compatible"
We should emit an error when [[intel::max_concurrency(k)]] and [[intel::fpga_pipeline(0)]] are used together:
"error: max_concurrency and fpga_pipeline(0) attributes are not compatible"
Note: this basically performs very similar functionalities as [[intel::disable_loop_pipelining]], the plan is to deprecate disable_loop_pipelining in future releases and use [[intel::fpga_pipeline(n)]] instead.
Signed-off-by: Soumi Manna <[email protected]>
Signed-off-by: Soumi Manna <[email protected]>
Signed-off-by: Soumi Manna <[email protected]>
Signed-off-by: Soumi Manna <[email protected]>
smanna12
commented
Jun 6, 2022
Signed-off-by: Soumi Manna <[email protected]>
|
Robert, Ho from PSG (or his delegate) will take over this review :) I have notified him. Removing myself from the review. |
premanandrao
reviewed
Jun 6, 2022
Signed-off-by: Soumi Manna <[email protected]>
Signed-off-by: Soumi Manna <[email protected]>
Thanks @premanandrao for taking a look at the patch. |
|
ping @premanandrao, @elizabethandrews. |
Signed-off-by: Soumi Manna <[email protected]>
Signed-off-by: Soumi Manna <[email protected]>
premanandrao
previously approved these changes
Jun 9, 2022
Signed-off-by: Soumi Manna <[email protected]>
Signed-off-by: Soumi Manna <[email protected]>
premanandrao
approved these changes
Jun 10, 2022
smanna12
added a commit
to smanna12/llvm
that referenced
this pull request
Jul 6, 2022
…ining attribute intel#6254 added the fpga_pipeline attribute and deprecated the intel::disable_loop_pipelining attribute. While this was in the pipeline, the internal decision was made to switch to properties rather than attributes for this type of thing. At this point, internal request is that (at a minimum) the deprecation message for intel::disable_loop_pipelining be removed, as we no longer plan to deprecate it. Signed-off-by: Soumi Manna <[email protected]>
steffenlarsen
pushed a commit
that referenced
this pull request
Jul 7, 2022
…ining attribute (#6404) #6254 added the fpga_pipeline attribute and deprecated the intel::disable_loop_pipelining attribute. While this was in the pipeline, the internal decision was made to switch to properties rather than attributes for this type of thing. At this point, internal request is that (at a minimum) the deprecation message for intel::disable_loop_pipelining be removed, as we no longer plan to deprecate it. Optionally the intel::fpga_pipeline attribute can be removed from the frontend as well. Signed-off-by: Soumi Manna <[email protected]>
smanna12
added a commit
to smanna12/llvm
that referenced
this pull request
Aug 2, 2022
Support for new FPGA attribute called [[intel::fpga_pipeline(N)]] on intel#6254 is no longer needed. This patch removes the support from frontend. Signed-off-by: Soumi Manna <[email protected]>
bader
pushed a commit
that referenced
this pull request
Aug 4, 2022
Support for new FPGA attribute called [[intel::fpga_pipeline(N)]] on #6254 is no longer needed. This patch removes the support from frontend. Signed-off-by: Soumi Manna <[email protected]>
raaiq1
pushed a commit
to raaiq1/llvm
that referenced
this pull request
Aug 4, 2022
…#6519) Support for new FPGA attribute called [[intel::fpga_pipeline(N)]] on intel#6254 is no longer needed. This patch removes the support from frontend. Signed-off-by: Soumi Manna <[email protected]>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This patch adds support for new FPGA attribute called [[intel::fpga_pipeline(N)]] that takes a Boolean parameter.
N can be a template parameter or constexpr. If the user didn't provide a parameter, the default value of N would
be 1, which implies enable pipelining.
This attribute can be applied to loops.
Example syntax:
// will disable loop pipelining
[[intel::fpga_pipeline(0)]]
for (int i = 0; i<N; ++i) {...}
LLVM IR:
When applied on a loop, the LLVM IR should be attached to llvm.loop metadata:
!{!"llvm.loop.intel.pipelining.enable", i32 N}
The value of the !"llvm.loop.intel.pipelining.enable" metadata is an i32 value that corresponds to the boolean parameter N.
A value of 0 is used for not pipelining the loop.
A value of 1 is used for pipelining the loop.
If the parameter is not given, value of N will be the default value 1, which implies we will pipeline the loop, and the IR will look like
!{!"llvm.loop.intel.pipelining.enable", i32 1}
Error Message:
We should emit an error when [[intel::initiation_interval(k)]] and [[intel::fpga_pipeline(0)]] are used together:
"error: initiation_interval and fpga_pipeline(0) attributes are not compatible"
We should emit an error when [[intel::max_concurrency(k)]] and [[intel::fpga_pipeline(0)]] are used together:
"error: max_concurrency and fpga_pipeline(0) attributes are not compatible"
Note: this basically performs very similar functionalities as [[intel::disable_loop_pipelining]], the plan is to deprecate disable_loop_pipelining in future releases and use [[intel::fpga_pipeline(n)]] instead.
Signed-off-by: Soumi Manna [email protected]