Skip to content

Vector register#293

Merged
lekcyjna123 merged 32 commits into
lekcyjna/big-vectorfrom
lekcyjna/vector_register
Jun 28, 2023
Merged

Vector register#293
lekcyjna123 merged 32 commits into
lekcyjna/big-vectorfrom
lekcyjna/vector_register

Conversation

@lekcyjna123
Copy link
Copy Markdown
Contributor

@lekcyjna123 lekcyjna123 commented Apr 18, 2023

After preparing high level schema of vector core I start the implementation with the implementation of very simple (and very not optimal) vector registers. Next step is to create a more "intelligent" implementation.

  • Continuous vector register with tests
  • Interlacing vector register with tests (in separate PR)
  • Split changes in utils to separate merge request
  • Add docs strings
  • Add support for scalars (in separate PR)

@lekcyjna123
Copy link
Copy Markdown
Contributor Author

I tried to implement inside VRRFragment a logic to make forwarding between reading methods e.g:

  • Let assume that we have two ports (p1 and p2)
  • We get request to read from v1 element on position x on both ports
  • In simple implementation this will take two cycles (first cycle to read by p1 and second to read by p2)
  • I tried to implement forwarding, so in case when the same element is read p1 read data from register and p2 copy read data from p1

Problem which I hit is that register is synchronous memory, so I need to have request - response pattern and I have to synchronize responses to have correct data forwarding from p1 to p2 (both p1 and p2 responses have to be called in the same cycle). I was able to write implication that p2 response is ready when p1 is run, but I don't see how to do that in the other way (I thought about some helper structures e.g buffers/fifos).

As for now I plan to drop this forwarding functionality and it will have to be handled either by unit reading register or there will be an additional cycle of delay. The other possibility was to leave only this implication, but this would be error prone due to timings dependency (both methods run in the same cycle).

@lekcyjna123 lekcyjna123 mentioned this pull request Apr 23, 2023
1 task
@tilk tilk added the enhancement New feature or request label Apr 26, 2023
@lekcyjna123 lekcyjna123 mentioned this pull request May 17, 2023
Lekcyjna and others added 2 commits May 17, 2023 17:38
Flexible adder

---------

Co-authored-by: Lekcyjna <309016@uwr.edu.pl>
@lekcyjna123 lekcyjna123 changed the base branch from master to lekcyjna/big-vector June 25, 2023 08:13
@lekcyjna123 lekcyjna123 marked this pull request as ready for review June 26, 2023 13:10
@lekcyjna123
Copy link
Copy Markdown
Contributor Author

Tomorrow I plan to add docstrings and merge it to development branch.

@lekcyjna123 lekcyjna123 merged commit 21ae65f into lekcyjna/big-vector Jun 28, 2023
@lekcyjna123 lekcyjna123 deleted the lekcyjna/vector_register branch June 28, 2023 10:01
lekcyjna123 pushed a commit that referenced this pull request Jun 28, 2023
Routings

Multiport fifo (#260)

Extend decoder with part of V instructions. (#396)

Vector register (#293)

---------

Co-authored-by: Lekcyjna <309016@uwr.edu.pl>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

enhancement New feature or request

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants