Extend decoder with part of V instructions.

[lekcyjna123]

Hi,

here is a part of V instructions which I plan to merge tomorrow to development branch. Most important change introduced by this commit is existence of new field in output of decoder "RegisterType", which indicates if register is scalar (X) or vector(V) in future this can be used to add support for floating point registers.

I have to add decoding tests before merge. They will be generated using llvm based on test/asm/v_instr.asm.

[tilk]

The idea is that this will influence register renaming, right?

[lekcyjna123]

Yes. In case when RegisterType will be X register will be renamed by scalar register renaming. In other cases it will be forwarded without changes to FU and in case of vector registers renaming will be done in vector FU.

Edit:
Other solution is to rename both types of registers in rename phase, but this will be a little more complicated, because we don't support injecting custom block to scheduler yet. So I decided to make vector renaming in FU and later as a improvement it can be moved to scheduler.

[lekcyjna123]

I have observed that adding decoding of 1/3 vector instructions to our current decoder extends simulation time by factor of 2 (calculated over tests which decodes instructions from extension I). So I started benchmarks for this PR without and with vector extension activated. It looks like my changes haven't big impact on Fmax (59MHz vs 57MHz), but in near future a decoder will need a great rework.

Without V:
https://github.com/kuznia-rdzeni/coreblocks/actions/runs/5391792933/jobs/9789181833
With V:
https://github.com/kuznia-rdzeni/coreblocks/actions/runs/5391851409/jobs/9789330046