Extend decoder with part of V instructions.

coreblocks/frontend/decode.py

@@ -53,8 +53,11 @@ def elaborate(self, platform):
                     "regs_l": {
                         # read/writes to phys reg 0 make no effect
                         "rl_dst": Mux(instr_decoder.rd_v, instr_decoder.rd, 0),
+                        "rl_dst_rf": Mux(instr_decoder.rd_v, instr_decoder.rd_rf, 0),
                         "rl_s1": Mux(instr_decoder.rs1_v, instr_decoder.rs1, 0),
+                        "rl_s1_rf" : Mux(instr_decoder.rs1_v, instr_decoder.rs1_rf, 0),
                         "rl_s2": Mux(instr_decoder.rs2_v, instr_decoder.rs2, 0),
+                        "rl_s2_rf" : Mux(instr_decoder.rs2_v, instr_decoder.rs2_rf, 0),
                     },
                     "imm": instr_decoder.imm,
                     "csr": instr_decoder.csr,

coreblocks/params/configurations.py

@@ -112,3 +112,6 @@ def replace(self, **kwargs):
     phys_regs_bits=7,
     _implied_extensions=Extension.I,
 )
+
+# Core configuration with vector extension
+vector_core_config = CoreConfiguration(_implied_extensions = Extension.V)

coreblocks/params/isa.py

@@ -6,12 +6,14 @@
     "InstrType",
     "Opcode",
     "Funct3",
+    "Funct6",
     "Funct7",
     "Funct12",
     "Extension",
     "FenceTarget",
     "FenceFm",
     "ISA",
+    "RegisterType",
 ]
 
 
@@ -23,34 +25,81 @@ class InstrType(Enum):
     B = 3
     U = 4
     J = 5
+    S1U = 6 # Unsigned imm in RS1 
+    S1I = 7 # Imm in RS1 
+    S1IS2 = 8 # Imm in RS1, valid RS2
 
 
 @unique
 class Opcode(IntEnum, shape=5):
+    LOAD = 0b00000
+    MISC_MEM = 0b00011
     OP_IMM = 0b00100
-    LUI = 0b01101
     AUIPC = 0b00101
+    STORE = 0b01000
     OP = 0b01100
+    LUI = 0b01101
     OP32 = 0b01110
-    JAL = 0b11011
-    JALR = 0b11001
+    OP_V = 0b10101
     BRANCH = 0b11000
-    LOAD = 0b00000
-    STORE = 0b01000
-    MISC_MEM = 0b00011
+    JALR = 0b11001
+    JAL = 0b11011
     SYSTEM = 0b11100
 
 
 class Funct3(IntEnum, shape=3):
-    JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = 0b000
-    BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL = SEXTB = SEXTH = CLMUL = 0b001
-    W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = 0b010
-    SLTU = CSRRC = MULHU = CLMULH = 0b011
-    BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = 0b100
-    BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = 0b101
-    BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = 0b110
-    BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = 0b111
-
+    JALR = BEQ = B = ADD = SUB = FENCE = PRIV = MUL = MULW = OPIVV = 0b000
+    BNE = H = SLL = FENCEI = CSRRW = MULH = BCLR = BINV = BSET = CLZ = CPOP = CTZ = ROL = SEXTB = SEXTH = CLMUL = OPFVV = 0b001
+    W = SLT = CSRRS = MULHSU = SH1ADD = CLMULR = OPMVV = 0b010
+    SLTU = CSRRC = MULHU = CLMULH = OPIVI = 0b011
+    BLT = BU = XOR = DIV = DIVW = SH2ADD = MIN = XNOR = ZEXTH = OPIVX = 0b100
+    BGE = HU = SR = CSRRWI = DIVU = DIVUW = BEXT = ORCB = REV8 = ROR = MINU = OPFVF = 0b101
+    BLTU = OR = CSRRSI = REM = REMW = SH3ADD = MAX = ORN = OPMVX = 0b110
+    BGEU = AND = CSRRCI = REMU = REMUW = ANDN = MAXU = OPCFG = 0b111
+
+class Funct6(IntEnum, shape=6):
+    VADD     = 0b000000
+    VSUB     = 0b000010
+    VRSUB    = 0b000011
+    VMINU    = 0b000100
+    VMIN     = 0b000101
+    VMAXU    = 0b000110
+    VMAX     = 0b000111
+    VAND     = 0b001001
+    VOR      = 0b001010
+    VXOR     = 0b001011
+    VRGATHER = 0b001100
+    VSLIDEUP = VRGATHEREI16 = 0b001110
+    VSLIDEDOWN=0b001111
+    VADC     = 0b010000
+    VMADC    = 0b010001
+    VSBC     = 0b010010
+    VMSBC    = 0b010011
+    VMERGE   = VMV = 0b010111
+    VMSEQ    = 0b011000
+    VMSNE    = 0b011001
+    VMSLTU   = 0b011010
+    VMSLT    = 0b011011
+    VMSLEU   = 0b011100
+    VMSLE    = 0b011101
+    VMSGTU   = 0b011110
+    VMSGT    = 0b011111
+    VSADDU   = 0b100000
+    VSADD    = 0b100001
+    VSSUBU   = 0b100010
+    VSSUB    = 0b100011
+    VSLL     = 0b100101
+    VSMUL    = VMV1R = VMV2R = VMV4R = VMV8R = 0b100111
+    VSRL     = 0b101000
+    VSRA     = 0b101001
+    VSSRL    = 0b101010
+    VSSRA    = 0b101011
+    VNSRL    = 0b101100
+    VNSRA    = 0b101101
+    VNCLIPU  = 0b101110
+    VNCLIP   = 0b101111
+    VWREDSUMU= 0b110000
+    VWREDSUM = 0b110001
 
 class Funct7(IntEnum, shape=7):
     SL = SLT = ADD = XOR = OR = AND = 0b0000000
@@ -96,6 +145,11 @@ class FenceFm(IntEnum, shape=4):
     NONE = 0b0000
     TSO = 0b1000
 
+@unique
+class RegisterType(IntEnum, shape=1):
+    X = 0b0
+    V = 0b1
+
 
 @unique
 class Extension(enum.IntFlag):

coreblocks/params/layouts.py

@@ -1,4 +1,4 @@
-from coreblocks.params import GenParams, OpType, Funct7, Funct3, Opcode
+from coreblocks.params import GenParams, OpType, Funct7, Funct3, Opcode, RegisterType
 from coreblocks.utils.utils import layout_subset
 
 __all__ = [
@@ -29,8 +29,11 @@ def __init__(self, gen_params: GenParams):
 
         self.regs_l = [
             ("rl_s1", gen_params.isa.reg_cnt_log),
+            ("rl_s1_rf", RegisterType),
             ("rl_s2", gen_params.isa.reg_cnt_log),
+            ("rl_s2_rf", RegisterType),
             ("rl_dst", gen_params.isa.reg_cnt_log),
+            ("rl_dst_rf", RegisterType),
         ]
 
         self.regs_p = [

coreblocks/params/optypes.py

@@ -42,6 +42,19 @@ class OpType(IntEnum):
     CLMUL = auto()
     SRET = auto()
     SFENCEVMA = auto()
+    V_ARITHMETIC = auto()
+    V_ARITHMETIC_IMM = auto()
+    V_ARITHMETIC_SCALAR = auto()
+    # TODO after V implementation check if there is a need for separate optype for narrowing
+    V_ARITHMETIC_NARROWING = auto()
+    V_ARITHMETIC_NARROWING_IMM = auto()
+    V_ARITHMETIC_NARROWING_SCALAR = auto()
+    V_PERMUTATION = auto()
+    V_PERMUTATION_IMM = auto()
+    V_PERMUTATION_SCALAR = auto()
+    V_CONTROL = auto()
+    V_REDUCTION = auto()
+
 
 
 #
@@ -103,6 +116,19 @@ class OpType(IntEnum):
         OpType.SRET,
         OpType.SFENCEVMA,
     ],
+    Extension.V: [
+        OpType.V_ARITHMETIC,
+        OpType.V_ARITHMETIC_IMM,
+        OpType.V_ARITHMETIC_SCALAR,
+        OpType.V_ARITHMETIC_NARROWING, 
+        OpType.V_ARITHMETIC_NARROWING_IMM, 
+        OpType.V_ARITHMETIC_NARROWING_SCALAR, 
+        OpType.V_PERMUTATION,
+        OpType.V_PERMUTATION_IMM,
+        OpType.V_PERMUTATION_SCALAR,
+        OpType.V_CONTROL,
+        OpType.V_REDUCTION,
+    ],
 }
 
 

scripts/synthesize.py

@@ -17,7 +17,7 @@
 from coreblocks.core import Core
 from coreblocks.transactions import TransactionModule
 from coreblocks.peripherals.wishbone import WishboneArbiter, WishboneBus
-from coreblocks.params.configurations import basic_core_config
+from coreblocks.params.configurations import basic_core_config, vector_core_config
 from constants.ecp5_platforms import make_ecp5_platform
 
 
@@ -51,7 +51,7 @@ def elaborate(self, platform: Platform):
 
 
 def synthesize(platform: str):
-    gen_params = GenParams(basic_core_config)
+    gen_params = GenParams(vector_core_config)
 
     if platform == "ecp5":
         make_ecp5_platform(gen_params.wb_params)().build(TestElaboratable(gen_params))

stubs/amaranth/lib/enum.pyi

@@ -3,6 +3,7 @@ This type stub file was generated by pyright.
 """
 
 import enum as py_enum
+from typing import overload, TypeVar
 from typing_extensions import Self
 from amaranth import *
 from ..hdl.ast import ShapeCastable
@@ -12,7 +13,7 @@ __all__ = ['EnumMeta', 'Enum', 'IntEnum', 'Flag', 'IntFlag', 'auto', 'unique']
 
 auto = py_enum.auto
 unique = py_enum.unique
-
+T = TypeVar('T')
 
 class EnumMeta(ShapeCastable, py_enum.EnumMeta):
     """Subclass of the standard :class:`enum.EnumMeta` that implements the :class:`ShapeCastable`
@@ -47,8 +48,15 @@ class EnumMeta(ShapeCastable, py_enum.EnumMeta):
             If the enumeration has neither an explicitly provided shape nor any members.
         """
         ...
+
+    @overload
+    def __call__(cls, value : Value) -> Value:
+        ...
+    @overload
+    def __call__(cls : type[T], value : int) -> T:
+        ...
 
-    def __call__(cls, value) -> Value:
+    def __call__(cls, value) -> Value | Self:
         ...
 
     def const(cls, init) -> Const:

test/asm/v_instr.asm

@@ -0,0 +1,122 @@
+# INTEGER
+# 0b00xxxx
+vadd.vv v1, v2, v3
+vadd.vv v1, v2, v3, v0.t
+vadd.vi v0, v4, 11
+vadd.vx v31, v8, x7
+vadd.vx v31, v8, x7, v0.t
+vsub.vv v4, v8, v3
+vsub.vx v2, v3, x1
+vrsub.vx v1, v2, x3
+vrsub.vi v1, v2, 7
+vminu.vv v1, v2, v3
+vminu.vx v1, v2, x3
+vmin.vv v1, v2, v3
+vmin.vx v1, v2, x3
+vmaxu.vv v1, v2, v3
+vmaxu.vx v1, v2, x3
+vmax.vv v1, v2, v3
+vmax.vx v1, v2, x3
+vand.vv v1, v2, v3
+vand.vx v1, v2, x3
+vand.vi v1, v2, 15
+vor.vv v1, v2, v3
+vor.vx v1, v2, x3
+vor.vi v1, v2, -16
+vxor.vv v1, v2, v3
+vxor.vx v1, v2, x3
+vxor.vi v1, v2, 0
+vrgather.vv v1, v2, v3
+vrgather.vx v1, v2, x3
+vrgather.vi v1, v2, 4
+vslideup.vx v1, v2, x3
+vslideup.vi v1, v2, 2
+vrgatherei16.vv v1, v2, v3
+vslidedown.vx v1, v2, x3
+vslidedown.vi v1, v2, 2
+
+# 0b01xxxx
+vadc.vvm v1, v2, v3, v0
+vadc.vxm v1, v2, x3, v0
+vadc.vim v1, v2, 3, v0
+vmadc.vvm v1, v2, v3, v0
+vmadc.vxm v1, v2, x3, v0
+vmadc.vim v1, v2, 3, v0
+vsbc.vvm v1, v2, v3, v0
+vsbc.vxm v1, v2, x3, v0
+vmsbc.vvm v1, v2, v3, v0
+vmsbc.vxm v1, v2, x3, v0
+vmerge.vvm v1, v2, v3, v0
+vmerge.vxm v1, v2, x3, v0
+vmerge.vim v1, v2, 3, v0
+vmv.v.v v1, v3
+vmv.v.x v1, x3
+vmv.v.i v1, 3
+vmseq.vv v1, v2, v3
+vmseq.vx v1, v2, x3
+vmseq.vi v1, v2, 3
+vmsne.vv v1, v2, v3
+vmsne.vx v1, v2, x3
+vmsne.vi v1, v2, 3
+vmsltu.vv v1, v2, v3
+vmsltu.vx v1, v2, x3
+vmslt.vv v1, v2, v3
+vmslt.vx v1, v2, x3
+vmsleu.vv v1, v2, v3
+vmsleu.vx v1, v2, x3
+vmsleu.vi v1, v2, 3
+vmsle.vv v1, v2, v3
+vmsle.vx v1, v2, x3
+vmsle.vi v1, v2, 3
+vmsgtu.vx v1, v2, x3
+vmsgtu.vi v1, v2, 3
+vmsgt.vx v1, v2, x3
+vmsgt.vi v1, v2, 3
+
+# 0b10xxxx
+vsaddu.vv v1, v2, v3
+vsaddu.vx v1, v2, x3
+vsaddu.vi v1, v2, 3
+vsadd.vv v1, v2, v3
+vsadd.vx v1, v2, x3
+vsadd.vi v1, v2, 3
+vssubu.vv v1, v2, v3
+vssubu.vx v1, v2, x3
+vssub.vv v1, v2, v3
+vssub.vx v1, v2, x3
+vsll.vv v1, v2, v3
+vsll.vx v1, v2, x3
+vsll.vi v1, v2, 3
+vsmul.vv v1, v2, v3
+vsmul.vx v1, v2, x3
+vmv1r.v v0, v8
+vmv2r.v v0, v8
+vmv4r.v v0, v8
+vmv8r.v v0, v8
+vsrl.vv v1, v2, v3
+vsrl.vx v1, v2, x3
+vsrl.vi v1, v2, 3
+vsra.vv v1, v2, v3
+vsra.vx v1, v2, x3
+vsra.vi v1, v2, 3
+vnsrl.wv v1, v2, v3
+vnsrl.wx v1, v2, x3
+vnsrl.wi v1, v2, 3
+vnsra.wv v1, v2, v3
+vnsra.wx v1, v2, x3
+vnsra.wi v1, v2, 3
+vnclipu.wv v1, v2, v3
+vnclipu.wx v1, v2, x3
+vnclipu.wi v1, v2, 3
+vnclip.wv v1, v2, v3
+vnclip.wx v1, v2, x3
+vnclip.wi v1, v2, 3
+
+#0b11xxxx
+vwredsumu.vs v1, v2, v3
+vwredsum.vs v1, v2, v3
+
+# CONTROL
+vsetvl x0, x1, x2
+vsetvli x0, x0, e32,m8,ta,ma
+vsetivli x1, 8, e32,m8,ta,ma