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Implement MMU#917

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qbojj wants to merge 20 commits intokuznia-rdzeni:masterfrom
qbojj:feat-mmu
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Implement MMU#917
qbojj wants to merge 20 commits intokuznia-rdzeni:masterfrom
qbojj:feat-mmu

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@qbojj qbojj commented Apr 26, 2026

Based on #884 and #916

Implement MMU featuring:

  • L1D and L1I TLB storing entries available for same-cycle translation - fully associative
  • L2 TLB - set-associative
  • PTW - implementing Svade samantics (Svadu would require LSU atomics redesign)

@tilk tilk added enhancement New feature or request microarch Involves the processor's microarchitecture and removed microarch Involves the processor's microarchitecture labels Apr 29, 2026
@qbojj qbojj added the nlnet The work is part of the NLnet grant label May 2, 2026
Comment thread coreblocks/priv/vmem/translation.py Outdated
Comment thread coreblocks/priv/vmem/translation.py Outdated
Comment thread coreblocks/priv/vmem/translation.py Outdated
Comment thread coreblocks/priv/vmem/walker.py Outdated
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