Add simulation logs options to gen_verilog#935
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awariac wants to merge 1 commit intokuznia-rdzeni:masterfrom
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Add simulation logs options to gen_verilog#935awariac wants to merge 1 commit intokuznia-rdzeni:masterfrom
awariac wants to merge 1 commit intokuznia-rdzeni:masterfrom
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Adds option for emitting print statements for transactron.lib.logging logs to work in external simulators like Verilator.
See kuznia-rdzeni/transactron#156