HDL logging wrappers#156
Conversation
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This is for use with other toolchains when integrating Coreblocks into larger systems? |
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Are you aware of any way to test this? I'm reluctant to include code not covered by any tests. |
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ok, found a way |
yes, it was useful when debugging Linux boot on Litex, using external Verilator simulation run |
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requires kuznia-rdzeni/amaranth-stubs#14 |
Merged and made a new release. |
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@tilk should stubs be updated to >= requirement instead of ~=? |
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Why? Actually the problem is your changes in |
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Re-published the new stubs as Also, I'm thinking of changing the versioning to follow |
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would |
Right, |
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@awariac: I have made two other changes to |
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looks like it works |
Module wrappers (similar to Transacti?Component) to enable HDL logging backend, e.g. synthesized to Verilog code (very useful!).
Conversion to Framgent is performed first, because it needs to force elaboration and add all log records to LogKey first.