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Update for Transactron 0.7#939

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tilk wants to merge 11 commits intokuznia-rdzeni:masterfrom
tilk:update-transactron-0.7
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Update for Transactron 0.7#939
tilk wants to merge 11 commits intokuznia-rdzeni:masterfrom
tilk:update-transactron-0.7

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@tilk
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@tilk tilk commented May 3, 2026

This PR makes changes necessary for the upcoming Transactron 0.7 release.

@tilk tilk added the refactor Doesn't change functionality, but makes stuff nicer label May 3, 2026
@tilk tilk added benchmark Benchmarks should be run for this change labels May 3, 2026
@tilk tilk force-pushed the update-transactron-0.7 branch from f532e22 to c388176 Compare May 3, 2026 15:52
@tilk tilk force-pushed the update-transactron-0.7 branch from c388176 to d40fb3a Compare May 3, 2026 17:16
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awariac commented May 4, 2026

Circular combinational logic: 'top.elaboratable.CheckpointRAT_rename0_run' oh no

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github-actions Bot commented May 4, 2026

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.431 (0.000) 0.554 (0.000) 0.382 (0.000) 0.653 (0.000) 0.361 (0.000) 0.305 (0.000) 0.331 (0.000) 0.450 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 18061 (-7) 4800 (0) ▲ 1382 (+32) 1372 (0) ▼ 49 (-1)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 49782 (-659) 10184 (0) ▲ 3582 (+58) 2636 (0) ▲ 36 (+2)

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tilk commented May 4, 2026

Circular combinational logic: 'top.elaboratable.CheckpointRAT_rename0_run' oh no

That was just a minor issue in argument validation.

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github-actions Bot commented May 6, 2026

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.431 (0.000) 0.554 (0.000) 0.382 (0.000) 0.653 (0.000) 0.361 (0.000) 0.305 (0.000) 0.331 (0.000) 0.450 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 18012 (-56) 4800 (0) ▲ 1382 (+32) 1372 (0) ▼ 46 (-4)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▲ 51018 (+577) 10184 (0) ▲ 3582 (+58) 2636 (0) ▲ 35 (+1)

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github-actions Bot commented May 6, 2026

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.431 (0.000) 0.554 (0.000) 0.382 (0.000) 0.653 (0.000) 0.361 (0.000) 0.305 (0.000) 0.331 (0.000) 0.450 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 17943 (-125) 4800 (0) 1350 (0) 1372 (0) ▲ 51 (+1)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▲ 50856 (+415) 10184 (0) ▲ 3550 (+26) 2636 (0) ▲ 37 (+2)

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