Update for Transactron 0.7

.github/workflows/deploy_gh_pages.yml

@@ -26,7 +26,7 @@ jobs:
       - name: Set up Python
         uses: actions/setup-python@v5
         with:
-          python-version: "3.11"
+          python-version: "3.13"
 
       - name: Install dependencies
         run: |

.github/workflows/main.yml

@@ -140,7 +140,7 @@ jobs:
     runs-on: ubuntu-22.04  # older version for compatibility with Docker image
     container: ghcr.io/kuznia-rdzeni/verilator:v5.008-2023.11.19_v
     needs: [ build-riscof-tests, build-core ]
-    timeout-minutes: 30
+    timeout-minutes: 45
     steps:
       - name: Checkout
         uses: actions/checkout@v6
@@ -304,7 +304,7 @@ jobs:
   unit-test:
     name: Run unit tests
     runs-on: ubuntu-latest
-    timeout-minutes: 60
+    timeout-minutes: 90
     steps:
       - name: Checkout
         uses: actions/checkout@v6

coreblocks/cache/icache.py

@@ -12,7 +12,7 @@
 from coreblocks.interface.layouts import ICacheLayouts
 from transactron.utils import assign, OneHotSwitchDynamic
 from transactron.lib import *
-from transactron.lib import logging
+from transactron.utils import logging
 from coreblocks.peripherals.bus_adapter import BusMasterInterface
 
 from coreblocks.cache.iface import CacheInterface, CacheRefillerInterface

coreblocks/core.py

@@ -64,9 +64,10 @@ def __init__(self, *, gen_params: GenParams):
 
         self.rf_allocator = PriorityEncoderAllocator(
             gen_params.phys_regs,
-            max(gen_params.frontend_superscalarity, gen_params.retirement_superscalarity),
+            gen_params.frontend_superscalarity,
+            gen_params.retirement_superscalarity,
             init=2**gen_params.phys_regs - 2,
-        )  # TODO: different ways for alloc and dealloc
+        )
 
         self.CRAT = CheckpointRAT(gen_params=self.gen_params)
         self.RRAT = RRAT(gen_params=self.gen_params)
@@ -145,7 +146,7 @@ def _():
 
         m.submodules.scheduler = scheduler = Scheduler(gen_params=self.gen_params)
         scheduler.get_instr.provide(get_instr)
-        scheduler.get_free_reg.provide(rf_allocator.alloc[: self.gen_params.frontend_superscalarity])
+        scheduler.get_free_reg.provide(rf_allocator.alloc)
         scheduler.crat_commit_checkpoint.provide(crat.commit_checkpoint)
         scheduler.crat_rename.provide(crat.rename)
         scheduler.crat_tag.provide(crat.tag)
@@ -179,7 +180,7 @@ def _():
         retirement.rob_retire.provide(rob.retire)
         retirement.r_rat_commit.provide(rrat.commit)
         retirement.r_rat_peek.provide(rrat.peek)
-        retirement.free_rf_put.provide(rf_allocator.free[: self.gen_params.retirement_superscalarity])
+        retirement.free_rf_put.provide(rf_allocator.free)
         retirement.rf_free.provide(rf.free)
         retirement.exception_cause_get.provide(self.exception_information_register.get)
         retirement.exception_cause_clear.provide(self.exception_information_register.clear)

coreblocks/core_structs/crat.py

@@ -3,7 +3,7 @@
 from amaranth.utils import ceil_log2
 
 from transactron.core import *
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.connectors import Pipe
 from transactron.lib.metrics import HwExpHistogram
 from transactron.lib.simultaneous import condition

coreblocks/core_structs/rf.py

@@ -5,7 +5,7 @@
 from transactron.utils.amaranth_ext.elaboratables import OneHotMux
 from coreblocks.interface.layouts import RFLayouts
 from coreblocks.params import GenParams
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.metrics import HwExpHistogram, TaggedLatencyMeasurer
 from transactron.lib.storage import MemoryBank
 from transactron.utils.amaranth_ext.functions import popcount

coreblocks/core_structs/rob.py

@@ -3,7 +3,7 @@
 from amaranth import *
 from transactron import Method, Methods, Transaction, def_method, TModule, def_methods
 from transactron.lib.fifo import WideFifo
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.metrics import *
 from transactron.utils import count_trailing_zeros
 from coreblocks.interface.layouts import ROBLayouts

coreblocks/frontend/fetch/fetch.py

@@ -1,10 +1,10 @@
 from math import lcm
 from amaranth import *
 from amaranth.lib.data import ArrayLayout
-from transactron.lib import BasicFifo, WideFifo, Semaphore, logging, Pipe
+from transactron.lib import BasicFifo, WideFifo, Semaphore, Pipe
 from transactron.lib.metrics import *
 from transactron.lib.simultaneous import condition
-from transactron.utils import count_trailing_zeros, popcount, assign, StableSelectingNetwork
+from transactron.utils import count_trailing_zeros, popcount, assign, StableSelectingNetwork, logging
 from transactron.utils.transactron_helpers import make_layout
 from transactron.utils.amaranth_ext.coding import PriorityEncoder
 from transactron import *

coreblocks/frontend/stall_controller.py

@@ -5,7 +5,7 @@
 from amaranth import *
 
 
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.metrics import *
 from transactron.lib.simultaneous import condition
 from transactron.utils import popcount, DependencyContext, MethodStruct

coreblocks/func_blocks/fu/common/rs.py

@@ -6,14 +6,14 @@
 from amaranth.utils import ceil_log2
 from amaranth_types import ValueLike
 from transactron import Method, Methods, Transaction, def_method, TModule, def_methods
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.allocators import PreservedOrderAllocator
 from transactron.utils.amaranth_ext.elaboratables import OneHotMux
 from coreblocks.params import GenParams
 from coreblocks.arch import OpType
 from coreblocks.interface.layouts import RSLayouts
 from transactron.lib.metrics import HwExpHistogram, TaggedLatencyMeasurer
-from transactron.utils import RecordDict
+from transactron.utils import ReturnDict
 from transactron.utils.assign import assign, AssignType
 from transactron.utils.amaranth_ext.functions import popcount
 from transactron.utils.transactron_helpers import make_layout
@@ -93,7 +93,7 @@ def _elaborate(self, m: TModule, takeable_mask: ValueLike, alloc: Method, free_i
             ready_lists.append(self.data_ready & op_vector)
 
         @def_method(m, self.select)
-        def _() -> RecordDict:
+        def _() -> ReturnDict:
             selected_id = alloc(m).ident
             self.log.debug(m, True, "selected entry {}", selected_id)
             return {"rs_entry_id": selected_id}
@@ -151,7 +151,7 @@ def _(rs_entry_id: Value, rs_data: Value) -> None:
             self.order = order(m).order  # always ready!
 
         @def_method(m, self.take)
-        def _(rs_entry_id: Value) -> RecordDict:
+        def _(rs_entry_id: Value) -> ReturnDict:
             actual_rs_entry_id = Signal.like(rs_entry_id)
             m.d.av_comb += actual_rs_entry_id.eq(self.order[rs_entry_id])
             record = self.data[actual_rs_entry_id]
@@ -168,7 +168,7 @@ def _(rs_entry_id: Value) -> RecordDict:
             reordered_list = Cat(tk_ready_list.bit_select(self.order[i], 1) for i in range(self.rs_entries))
 
             @def_method(m, get_ready_list, ready=tk_ready_list.any(), nonexclusive=True)
-            def _() -> RecordDict:
+            def _() -> ReturnDict:
                 return {"ready_list": reordered_list}
 
         if self.perf_num_full.metrics_enabled():

coreblocks/func_blocks/fu/jumpbranch.py

@@ -8,7 +8,7 @@
 from transactron import *
 from transactron.core import def_method
 from transactron.lib import *
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.utils import DependencyContext, from_method_layout
 from coreblocks.params import GenParams, FunctionalComponentParams
 from coreblocks.arch import Funct3, OpType, ExceptionCause, Extension

coreblocks/func_blocks/fu/lsu/dummyLsu.py

@@ -3,7 +3,7 @@
 from amaranth import *
 from transactron import Method, TModule, Transaction, def_method
 from transactron.lib.connectors import FIFO, ConnectTrans
-from transactron.lib.logging import HardwareLogger
+from transactron.utils import logging
 from transactron.lib.simultaneous import condition
 from transactron.utils import DependencyContext
 
@@ -57,7 +57,7 @@ def __init__(self, gen_params: GenParams, bus: BusMasterInterface) -> None:
 
         self.bus = bus
 
-        self.log = HardwareLogger("backend.lsu.dummylsu")
+        self.log = logging.HardwareLogger("backend.lsu.dummylsu")
 
     def elaborate(self, platform):
         m = TModule()

coreblocks/func_blocks/fu/lsu/lsu_requester.py

@@ -2,7 +2,7 @@
 from amaranth_types import ModuleLike
 from transactron import Method, def_method, TModule
 from transactron.lib.simultaneous import condition
-from transactron.lib.logging import HardwareLogger
+from transactron.utils import logging
 from transactron.lib import BasicFifo
 
 from coreblocks.params import *
@@ -45,7 +45,7 @@ def __init__(self, gen_params: GenParams, bus: BusMasterInterface, depth: int =
         self.issue = Method(i=lsu_layouts.issue, o=lsu_layouts.issue_out)
         self.accept = Method(o=lsu_layouts.accept)
 
-        self.log = HardwareLogger("backend.lsu.requester")
+        self.log = logging.HardwareLogger("backend.lsu.requester")
 
     def prepare_bytes_mask(self, m: ModuleLike, funct3: Value, addr: Value) -> Signal:
         mask_len = self.gen_params.isa.xlen // self.bus.params.granularity

coreblocks/func_blocks/fu/priv.py

@@ -8,7 +8,7 @@
 
 
 from transactron import *
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.metrics import TaggedCounter
 from transactron.lib.simultaneous import condition
 from transactron.utils import DependencyContext, OneHotSwitch

coreblocks/peripherals/wishbone.py

@@ -11,7 +11,7 @@
 from transactron.utils.amaranth_ext.component_interface import ComponentInterface, CIn, COut
 from transactron.lib.connectors import Forwarder
 from transactron.utils.transactron_helpers import make_layout
-from transactron.lib import logging
+from transactron.utils import logging
 
 
 class WishboneParameters:

coreblocks/priv/csr/csr_instances.py

@@ -23,8 +23,7 @@
 from typing import Optional
 from amaranth.lib import data
 from transactron.core import Transaction, TModule
-from transactron.utils import DependencyContext
-from transactron.lib import logging
+from transactron.utils import DependencyContext, logging
 
 
 log = logging.HardwareLogger("priv.csr.instances")

coreblocks/priv/csr/shadow.py

@@ -7,8 +7,7 @@
 from transactron.core.transaction import Transaction
 from transactron.core.sugar import def_method
 from transactron.core.tmodule import TModule
-from transactron.utils import get_src_loc
-from transactron.lib import logging
+from transactron.utils import get_src_loc, logging
 
 from coreblocks.params.genparams import GenParams
 from coreblocks.priv.csr.csr_register import CSRRegisterBase

coreblocks/priv/traps/interrupt_controller.py

@@ -17,7 +17,7 @@
 
 from transactron.core import Method, TModule, def_method
 from transactron.core.transaction import Transaction
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.utils.dependencies import DependencyContext
 
 log = logging.HardwareLogger("core.interrupt_controller")

coreblocks/scheduler/scheduler.py

@@ -4,7 +4,7 @@
 
 from transactron import Method, Methods, Required, Transaction, TModule
 from transactron.lib import Connect, Pipe, WideFifo
-from transactron.lib import logging
+from transactron.utils import logging
 from transactron.lib.metrics import TaggedCounter
 from transactron.utils import OneHotSwitchDynamic, assign, AssignType
 from transactron.utils.dependencies import DependencyContext

docs/conf.py

@@ -1,13 +1,9 @@
 import datetime
-from sphinx_rtd_theme import get_html_theme_path
 
 # -- General configuration -----------------------------------------------------
 
 general_theme = "sphinx_rtd_theme"
 
-# Documentation theme.
-theme_path = get_html_theme_path() + "/" + general_theme
-
 # Minimal Sphinx version.
 needs_sphinx = "5.1.0"
 

pyproject.toml

@@ -17,11 +17,11 @@ classifiers = [
     "Topic :: Scientific/Engineering",
 ]
 dependencies = [
-    "amaranth==0.5.8",
-    "amaranth-stubs==0.1.2",
+    "amaranth~=0.5.8",
+    "amaranth-stubs~=0.5.0.0",
     "amaranth-yosys==0.40.0.0.post100",
     "dataclasses-json==0.6.3",
-    "transactron==0.6.1",
+    "transactron @ git+https://github.com/tilk/transactron@0ca55ff3a92054db908a1972c3f28c0d3ba813ae",
 ]
 
 [project.urls]
@@ -32,27 +32,31 @@ Issues = "https://github.com/kuznia-rdzeni/coreblocks/issues"
 
 [project.optional-dependencies]
 dev = [
-    "black==24.4.2",
-    "docutils==0.15.2",
+    # Linting
+    "pyright==1.1.393",
     "flake8==7.0.0",
-    "pep8-naming==0.13.3",
-    "markupsafe==2.0.1",
-    "myst-parser==0.18.0",
-    "numpydoc==1.5.0",
+    "black==24.4.2",
+    # Testing
+    "pytest==8.0.0",
+    "pytest-xdist==3.5.0",
+    "hypothesis==6.99.6",
     "parameterized==0.8.1",
-    "pre-commit==2.16.0",
-    "pyright==1.1.393",
-    "Sphinx==5.1.1",
-    "sphinx-rtd-theme==1.0.0",
-    "sphinxcontrib-mermaid==0.8.1",
     "cocotb==1.9.2",
     "cocotb-bus==0.2.1",
-    "pytest==8.0.0",
-    "pytest-xdist==3.5.0",
+    "docutils==0.21.2",
+    "markupsafe==2.0.1",
+    # Documentation
+    "pep8-naming==0.13.3",
+    "Sphinx==8.2.3",
+    "sphinx-rtd-theme==3.0.2",
+    "myst-parser==4.0.1",
+    "numpydoc==1.5.0",
+    "sphinxcontrib-mermaid==0.8.1",
+    # Other
+    "pre-commit==2.16.0",
     "pyelftools==0.29",
     "tabulate==0.9.0",
     "filelock==3.13.1",
-    "hypothesis==6.99.6",
 ]
 
 [tool.setuptools.packages.find]

test/func_blocks/fu/functional_common.py

@@ -19,7 +19,7 @@
 from coreblocks.arch.optypes import OpType
 from transactron.lib import Adapter
 from transactron.testing import (
-    RecordIntDict,
+    NameIntDict,
     TestbenchIO,
     TestCaseWithSimulator,
     SimpleTestCircuit,
@@ -117,9 +117,9 @@ def setup(self, fixture_initialize_testing_env):
         self.circ = ModuleConnector(dut=self.m, report_mock=self.report_mock, csrs=self.csrs)
 
         random.seed(self.seed)
-        self.requests = deque[RecordIntDict]()
-        self.responses = deque[RecordIntDict]()
-        self.exceptions = deque[RecordIntDict]()
+        self.requests = deque[NameIntDict]()
+        self.responses = deque[NameIntDict]()
+        self.exceptions = deque[NameIntDict]()
 
         max_int = 2**self.gen_params.isa.xlen - 1
         functions = list(self.ops.keys())

test/scheduler/test_wakeup_select.py

@@ -13,7 +13,7 @@
 from transactron import *
 from coreblocks.scheduler.wakeup_select import *
 
-from transactron.testing import RecordIntDict, SimpleTestCircuit, TestCaseWithSimulator, TestbenchContext
+from transactron.testing import NameIntDict, SimpleTestCircuit, TestCaseWithSimulator, TestbenchContext
 from transactron.testing.functions import data_const_to_dict
 
 
@@ -30,7 +30,7 @@ def setup_method(self):
 
         random.seed(42)
 
-    def random_entry(self, layout: StructLayout) -> RecordIntDict:
+    def random_entry(self, layout: StructLayout) -> NameIntDict:
         result = {}
         for key, width_or_layout in layout.members.items():
             if isinstance(width_or_layout, int):
@@ -41,7 +41,7 @@ def random_entry(self, layout: StructLayout) -> RecordIntDict:
                 result[key] = self.random_entry(width_or_layout)
         return result
 
-    def maybe_insert(self, rs: list[Optional[RecordIntDict]]):
+    def maybe_insert(self, rs: list[Optional[NameIntDict]]):
         empty_entries = sum(1 for entry in rs if entry is None)
         if empty_entries > 0 and random.random() < 0.5:
             empty_idx = random.randrange(empty_entries)
@@ -56,7 +56,7 @@ def maybe_insert(self, rs: list[Optional[RecordIntDict]]):
     async def process(self, sim: TestbenchContext):
         inserted_count = 0
         issued_count = 0
-        rs: list[Optional[RecordIntDict]] = [None for _ in range(self.gen_params.max_rs_entries)]
+        rs: list[Optional[NameIntDict]] = [None for _ in range(self.gen_params.max_rs_entries)]
 
         self.m.take_row.enable(sim)
         self.m.issue.enable(sim)