[AMDGPU] Enable atomic optimizer for 64 bit divergent values #96473
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…ing for generic types
…ring for generic types
vikramRH
requested review from
jayfoad,
arsenm,
b-sumner,
pravinjagtap and
cdevadas
vikramRH
changed the title
If you're going to repost with a pre-commit, it would be better to have all the pieces squashed into one. Also you could look into using graphite or SPR for managing dependent pull requests |
arsenm
reviewed
Jun 25, 2024
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Apologies for the commit spam here, graphite seems a good option hereon. However all dependent patches have landed, the diff here is now up to date. |
jayfoad
reviewed
Jun 26, 2024
| @@ -402,34 +413,30 @@ Value *AMDGPUAtomicOptimizerImpl::buildReduction(IRBuilder<> &B, | |||
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| // Reduce within each pair of rows (i.e. 32 lanes). | |||
| assert(ST->hasPermLaneX16()); | |||
| V = B.CreateBitCast(V, IntNTy); | |||
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Please submit an NFC cleanup patch that just removes unnecessary bitcasting, before adding support for new atomic operations.
arsenm
reviewed
Jun 26, 2024
| case Type::IntegerTyID: { | ||
| if (Ty->getIntegerBitWidth() == 32 || Ty->getIntegerBitWidth() == 64) | ||
| return true; | ||
| } |
arsenm
reviewed
Jun 26, 2024
| @@ -178,6 +178,20 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) { | |||
| return Changed; | |||
| } | |||
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| static bool shouldOptimize(Type *Ty) { | |||
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Better name that expresses why this type is handleable.
Also in a follow up, really should cover the i16/half/bfloat and 2 x half, 2 x bfloat cases
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Kindly review only the top commit here, all the remaining changes are the same as in #89217 and #92725.
This is the final patch in the series.