Skip to content

Fix incorrect rs2 register read enable for immediate (OP_IMM) instructions #2394

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
Anubhav-30 wants to merge 1 commit into from
+25 −0
Closed

Fix incorrect rs2 register read enable for immediate (OP_IMM) instructions #2394

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
24 changes: 24 additions & 0 deletions dv/dv/tb_imm_rf_read.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
module tb_imm_rf_read;

logic rf_ren_a_o, rf_ren_b_o;

initial begin
$display("Testing IMM RF read...");

// Simulate expected behavior of OP_IMM
rf_ren_a_o = 1;
rf_ren_b_o = 0;

#1;

if (rf_ren_a_o !== 1)
$error("FAIL: rs1 should be enabled");

if (rf_ren_b_o !== 0)
$error("FAIL: rs2 should NOT be enabled");

$display("✅ PASS");
$finish;
end

endmodule
1 change: 1 addition & 0 deletions rtl/ibex_decoder.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -352,6 +352,7 @@ module ibex_decoder #(

OPCODE_OP_IMM: begin // Register-Immediate ALU Operations
rf_ren_a_o = 1'b1;
rf_ren_b_o = 1'b0;
rf_we = 1'b1;

unique case (instr[14:12])
Expand Down