DRAFT: Top-level DV: connect JTAG #75
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This commit connects the JTAG agent, monitor and other UVM components to get going with RV_DM top-level DV. Currently this commit is marked as draft because I'm getting the following error when running any top-level test ``` UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:75) [cfg] Looking for image for memory ChipMemSRAM with plus arg ChipMemSRAM_image_file=%s UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:80) [cfg] Got image file /home/mvdmaas/repos/chip-sunburst/scratch_sw/bare_metal/build/checks/chip_check.vmem for memory ChipMemSRAM UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:75) [cfg] Looking for image for memory ChipMemROM with plus arg ChipMemROM_image_file=%s UVM_INFO @ 0: (top_chip_dv_env_cfg.sv:75) [cfg] Looking for image for memory ChipMemUsbdevBuf with plus arg ChipMemUsbdevBuf_image_file=%s UVM_FATAL @ 0: (uvm_reg_block.svh:1093) [RegModel] Register model requires that UVM_REG_DATA_WIDTH be defined as 41 or greater. Currently defined as 32 ```
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I've found out that the error happens when creating the |
The `jtag_dtm_reg_dmi` register is 41 bits wide, so we need a wider `UVM_REG_DATA_WIDTH` than the 32 specified in *common_sim_cfg.hjson*. OpenTitan currently takes the approach of overriding `tl_dw` in the chip-level sim cfg HJSON file to achieve this, which we shall replicate.
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This commit connects the JTAG agent, monitor and other UVM components to get going with RV_DM top-level DV.
Currently this commit is marked as draft because I'm getting the following error when running any top-level test