DRAFT: Top-level DV: connect JTAG

hw/top_chip/dv/env/top_chip_dv_env.core

@@ -14,10 +14,10 @@ filesets:
       - lowrisc:dv:sw_logger_if
       - lowrisc:dv:mem_bkdr_util
       - lowrisc:dv:i2c_agent
+      - lowrisc:dv:jtag_agent
       - lowrisc:dv:spi_agent
       - lowrisc:dv:pattgen_agent
       - lowrisc:dv:uart_agent
-      - lowrisc:dv:jtag_agent
       - lowrisc:dv:pins_if
       - lowrisc:dv:common_ifs
     files:

hw/top_chip/dv/env/top_chip_dv_env.sv

@@ -15,6 +15,7 @@ class top_chip_dv_env extends uvm_env;
 
   // Agents
   i2c_agent     m_i2c_agents[NI2cs];
+  jtag_agent    m_jtag_agent;
   pattgen_agent m_pattgen_agent;
   spi_agent     m_spi_device_agents[NSpis];
   uart_agent    m_uart_agents[NUarts];
@@ -64,9 +65,13 @@ class top_chip_dv_env extends uvm_env;
     // Instantiate I^2C agents
     foreach (m_i2c_agents[i]) begin
       m_i2c_agents[i] = i2c_agent::type_id::create($sformatf("m_i2c_agent%0d", i), this);
-      uvm_config_db#(i2c_agent_cfg)::set(this, $sformatf("m_i2c_agent%0d*", i), "cfg",cfg.m_i2c_agent_cfgs[i]);
+      uvm_config_db#(i2c_agent_cfg)::set(this, $sformatf("m_i2c_agent%0d*", i), "cfg", cfg.m_i2c_agent_cfgs[i]);
     end
 
+    // Instantiate JTAG agent
+    m_jtag_agent = jtag_agent::type_id::create("m_jtag_agent", this);
+    uvm_config_db#(jtag_agent_cfg)::set(this, "m_jtag_agent*", "cfg", cfg.m_jtag_agent_cfg);
+
     // Instantiate pattgen agent
     m_pattgen_agent = pattgen_agent::type_id::create("m_pattgen_agent", this);
     uvm_config_db#(pattgen_agent_cfg)::set(this, "m_pattgen_agent*", "cfg", cfg.m_pattgen_agent_cfg);
@@ -100,6 +105,7 @@ class top_chip_dv_env extends uvm_env;
     foreach (m_i2c_agents[i]) begin
       virtual_sequencer.i2c_sequencer_hs[i] = m_i2c_agents[i].sequencer;
     end
+    virtual_sequencer.jtag_sequencer_hs = m_jtag_agent.sequencer;
     foreach (m_spi_device_agents[i]) begin
       virtual_sequencer.spi_device_sequencer_hs[i] = m_spi_device_agents[i].sequencer;
     end
@@ -112,6 +118,7 @@ class top_chip_dv_env extends uvm_env;
     foreach (m_i2c_agents[i]) begin
       m_i2c_agents[i].monitor.controller_mode_rd_item_port.connect(virtual_sequencer.i2c_rd_fifos[i].analysis_export);
     end
+    m_jtag_agent.monitor.analysis_port.connect(virtual_sequencer.jtag_rx_fifo.analysis_export);
     for (int i = 0; i < NUM_PATTGEN_CHANNELS; i++) begin
       m_pattgen_agent.monitor.item_port[i].connect(virtual_sequencer.pattgen_rx_fifo[i].analysis_export);
     end

hw/top_chip/dv/env/top_chip_dv_env_cfg.sv

@@ -16,6 +16,7 @@ class top_chip_dv_env_cfg extends uvm_object;
 
   // External interface agent configs
   rand i2c_agent_cfg     m_i2c_agent_cfgs[NI2cs];
+  rand jtag_agent_cfg    m_jtag_agent_cfg;
   rand pattgen_agent_cfg m_pattgen_agent_cfg;
   rand spi_agent_cfg     m_spi_device_agent_cfgs[NSpis];
   rand uart_agent_cfg    m_uart_agent_cfgs[NUarts];
@@ -28,6 +29,7 @@ class top_chip_dv_env_cfg extends uvm_object;
   endfunction
 
   virtual function void initialize();
+    `uvm_info(`gfn, "top_chip_env_cfg.initialize() start", UVM_LOW);
     get_mem_image_files_from_plusargs();
 
     // create i2c agent config obj
@@ -37,6 +39,13 @@ class top_chip_dv_env_cfg extends uvm_object;
       m_i2c_agent_cfgs[i].en_monitor = 1'b0;
     end
 
+    `uvm_info(`gfn, "m_jtag_agent_cfg::create() start", UVM_LOW);
+    // create jtag agent config obj
+    m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg");
+    m_jtag_agent_cfg.if_mode = dv_utils_pkg::Host;
+    m_jtag_agent_cfg.is_active = 1'b1;
+    `uvm_info(`gfn, "m_jtag_agent_cfg::create() end", UVM_LOW);
+
     // create pattgen agent config obj
     m_pattgen_agent_cfg = pattgen_agent_cfg::type_id::create("m_pattgen_agent_cfg");
     m_pattgen_agent_cfg.if_mode = Device;
@@ -59,6 +68,8 @@ class top_chip_dv_env_cfg extends uvm_object;
       m_uart_agent_cfgs[i].en_tx_monitor = 0;
       m_uart_agent_cfgs[i].en_rx_monitor = 0;
     end
+
+    `uvm_info(`gfn, "top_chip_env_cfg.initialize() end", UVM_LOW);
   endfunction
 
   function void get_mem_image_files_from_plusargs();

hw/top_chip/dv/env/top_chip_dv_env_pkg.sv

@@ -7,8 +7,9 @@ package top_chip_dv_env_pkg;
   import dv_utils_pkg::*;
   import mem_bkdr_util_pkg::*;
   import i2c_agent_pkg::*;
-  import spi_agent_pkg::*;
+  import jtag_agent_pkg::*;
   import pattgen_agent_pkg::*;
+  import spi_agent_pkg::*;
   import uart_agent_pkg::*;
 
   // macro includes

hw/top_chip/dv/env/top_chip_dv_virtual_sequencer.sv

@@ -14,19 +14,22 @@ class top_chip_dv_virtual_sequencer extends uvm_sequencer;
   // Handles to specific interface agent sequencers. Used by some virtual
   // sequences to drive RX (to-chip) items.
   i2c_sequencer        i2c_sequencer_hs[NI2cs];
+  jtag_sequencer       jtag_sequencer_hs;
   spi_sequencer        spi_device_sequencer_hs[NSpis];
   uart_sequencer       uart_sequencer_hs[NUarts];
 
   // FIFOs for monitor output. Used by some virtual sequences to check
   // TX (from-chip) items.
   uvm_tlm_analysis_fifo #(i2c_item)     i2c_rd_fifos[NI2cs];
+  uvm_tlm_analysis_fifo #(jtag_item)    jtag_rx_fifo;
   uvm_tlm_analysis_fifo #(pattgen_item) pattgen_rx_fifo[NUM_PATTGEN_CHANNELS];
   uvm_tlm_analysis_fifo #(uart_item)    uart_tx_fifos[NUarts];
 
   function void build_phase(uvm_phase phase);
     super.build_phase(phase);
     // Construct monitor output FIFOs
     foreach (i2c_rd_fifos[i]) i2c_rd_fifos[i] = new($sformatf("i2c_rd_fifo%0d", i), this);
+    jtag_rx_fifo = new("jtag_rx_fifo", this);
     foreach (pattgen_rx_fifo[i]) pattgen_rx_fifo[i] = new($sformatf("pattgen_rx_fifo%0d", i), this);
     foreach (uart_tx_fifos[i]) uart_tx_fifos[i] = new($sformatf("uart_tx_fifo%0d", i), this);
   endfunction

hw/top_chip/dv/top_chip_sim_cfg.hjson

@@ -26,6 +26,19 @@
       "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"
   ]
 
+  // Override existing project defaults to supply chip-specific values.
+  overrides: [
+    // The jtag agent requires the data and bytenable widths to be increased.
+    {
+      name: tl_dw
+      value: 64
+    }
+    {
+      name: tl_dbw
+      value: 8
+    }
+  ]
+
   sim_tops: [""]
 
   build_opts: ["+define+RVFI=1"]

hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_agent_cfg.sv

@@ -41,15 +41,22 @@ class jtag_agent_cfg extends dv_base_agent_cfg;
 
   function new (string name = "");
     super.new(name);
+    `uvm_info(`gfn, "jtag_agent_cfg.new() start", UVM_LOW);
     jtag_if_connected = new();
     // Create the JTAG DTM RAL.
+    `uvm_info(`gfn, "jtag_dtm_reg_block::create()", UVM_LOW);
     jtag_dtm_ral = jtag_dtm_reg_block::type_id::create("jtag_dtm_ral");
+    `uvm_info(`gfn, "jtag_dtm_ral.build()", UVM_LOW);
     jtag_dtm_ral.build(.base_addr(0), .csr_excl(null));
     jtag_dtm_ral.set_supports_byte_enable(1'b0);
+    `uvm_info(`gfn, "jtag_dtm_ral.lock_model()", UVM_LOW);
     jtag_dtm_ral.lock_model();
+    `uvm_info(`gfn, "jtag_dtm_ral.compute_mapped_addr_ranges()", UVM_LOW);
     jtag_dtm_ral.compute_mapped_addr_ranges();
+    `uvm_info(`gfn, "jtag_dtm_ral.compute_unmapped_addr_ranges()", UVM_LOW);
     jtag_dtm_ral.compute_unmapped_addr_ranges();
     // TODO: fix the computation of mapped and unmapped ranges.
+    `uvm_info(`gfn, "jtag_agent_cfg.new() end", UVM_LOW);
   endfunction : new
 
 endclass

hw/vendor/lowrisc_ip/dv/sv/jtag_agent/jtag_dtm_reg_block.sv

@@ -372,6 +372,7 @@ class jtag_dtm_reg_block extends dv_base_reg_block;
 
   virtual function void build(uvm_reg_addr_t base_addr,
                               csr_excl_item csr_excl = null);
+    `uvm_info(`gfn, $sformatf("jtag_dtm_reg_block::build() JTAG_DRW %d", JTAG_DRW), UVM_LOW);
     // create default map
     this.default_map = create_map(.name("default_map"),
                                   .base_addr(base_addr),