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feat: added page_read_chip and page_controller #29
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Mostly cosmetic changes requested. Can merge after addressing.
The main other change (for another PR) is that we need a slightly different version to handle indexed pages - these are where the key are several columns that are part of the cached trace, and we don't have an auto-generate index starting from 0.
I think there will be use cases for both, but not sure how to best refactor to make things as modular as possible. This is something to keep in mind when writing the read/write chip.
In other words, the current index
column with the constraint that it auto-increments by 1, is not needed if the page itself has columns for keys. One option is to make that index column optional, and configurable in the chip constructor.
@OsamaAlkhodairy for future use, and to stabilize the Page interface, let's add the cached trace commitment of the page as a public value to the PageReadChip. However this requires being able to convert |
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LGTM, change some debug prints to log
* feat: added page_read_chip and page_controller * fix: rust lint * fix: rust lint * chore: small edits * chore: updating to use the engine * chore: fixing imports * wip * feat: storing commitment in page_controller and other fixes * fix: adding tracing
…ications (#29) * [fix] Fix P256 `GENERATOR` and `double_impl` (#2) * fix p256-generator * add host tests for ecc * Use private repo for stark-backend (#11) * temp(ci): switch riscv AMI for runner (#14) * [chore] Update DSL verify to match plonky3 (#5) * Update DSL verify to match plonky3 * fix: transpose state for p3-keccak tracegen * chore: add comment linking plonky3 issue * Update stark-backend commit --------- Co-authored-by: Jonathan Wang <[email protected]> * Use full commit in openvm-stark-backend revision (#18) * chore: update `stark-backend` commit (#19) * [fix] `Rv32BaseAluAdapterAir` unconstrained register reads (#25) * Create pull_request_template.md (#26) * [fix] Poseidon2 verify_batch opcode can send to execution bus for invalid rows (#17) * [fix] Rust memory allocation overflow (#13) * Fix and add test * Fix lint error * Update crates/toolchain/platform/src/memory.rs --------- Co-authored-by: Jonathan Wang <[email protected]> * [fix] Constrain `final_hash` in sha256 air to address audit finding (#12) * [fix] properly constrain final_hash in sha256 air * Add negative test for underconstrained final_hash. It was manually checked that this new test would have passed before the change. * [fix] IsLtArraySubAir (#9) * add fix * add tests * remove diff_val * chore: update comment * chore: no try_inverse --------- Co-authored-by: Jonathan Wang <[email protected]> * [fix] `Rv32BaseAluAdapterAir` immediate limbs not range-checked (#8) * fix local_as2 * range check imm limbs * add count for range check * add test for unconstrained imm limb * fix MemoryTester chip trace height * add test for unconstrained rs2 read * Revert "fix local_as2" This reverts commit ef83121bf1796874affaca4682dbb4f9f051b079. * Revert "add count for range check" This reverts commit 5252444dfeaf41e7c336648ad92c4736f48ead9d. * Revert "range check imm limbs" This reverts commit 2e2937536069ae66849fdf7bba9ea509065d17fe. * fix unconstrained imm limbs * fix local_rs2_as test * fix lint * Update extensions/rv32im/circuit/src/base_alu/tests.rs --------- Co-authored-by: Jonathan Wang <[email protected]> * fix: fixed SHA2 subair trace generation and the testing (#28) * fix: loadstore sign of immediate (#4) * [fix] Fix P256 `GENERATOR` and `double_impl` (#2) * fix p256-generator * add host tests for ecc * fix: loadstore sign of immediate * fix: prints and test * fix: load_sign_extend tests * Update docs/specs/ISA.md * clarify notation and sign extension in ISA spec * fix reveal transpiler spec --------- Co-authored-by: Manh Dinh <[email protected]> Co-authored-by: Jonathan Wang <[email protected]> * fix transpiler * fix loadstore adapter * fix store transpiler * fix tests * add e2e test * fix docs * fix: jalr imm_sign (#30) * optimize record struct packing * chore: use from_bool * chore: derive_more feature in bench * fix bench * fix --------- Co-authored-by: Xinding Wei <[email protected]> Co-authored-by: Jonathan Wang <[email protected]> Co-authored-by: Golovanov399 <[email protected]> Co-authored-by: Avaneesh-axiom <[email protected]> Co-authored-by: Arayi Khalatyan <[email protected]>
…ications (#29) * [fix] Fix P256 `GENERATOR` and `double_impl` (#2) * fix p256-generator * add host tests for ecc * Use private repo for stark-backend (#11) * temp(ci): switch riscv AMI for runner (#14) * [chore] Update DSL verify to match plonky3 (#5) * Update DSL verify to match plonky3 * fix: transpose state for p3-keccak tracegen * chore: add comment linking plonky3 issue * Update stark-backend commit --------- Co-authored-by: Jonathan Wang <[email protected]> * Use full commit in openvm-stark-backend revision (#18) * chore: update `stark-backend` commit (#19) * [fix] `Rv32BaseAluAdapterAir` unconstrained register reads (#25) * Create pull_request_template.md (#26) * [fix] Poseidon2 verify_batch opcode can send to execution bus for invalid rows (#17) * [fix] Rust memory allocation overflow (#13) * Fix and add test * Fix lint error * Update crates/toolchain/platform/src/memory.rs --------- Co-authored-by: Jonathan Wang <[email protected]> * [fix] Constrain `final_hash` in sha256 air to address audit finding (#12) * [fix] properly constrain final_hash in sha256 air * Add negative test for underconstrained final_hash. It was manually checked that this new test would have passed before the change. * [fix] IsLtArraySubAir (#9) * add fix * add tests * remove diff_val * chore: update comment * chore: no try_inverse --------- Co-authored-by: Jonathan Wang <[email protected]> * [fix] `Rv32BaseAluAdapterAir` immediate limbs not range-checked (#8) * fix local_as2 * range check imm limbs * add count for range check * add test for unconstrained imm limb * fix MemoryTester chip trace height * add test for unconstrained rs2 read * Revert "fix local_as2" This reverts commit ef83121bf1796874affaca4682dbb4f9f051b079. * Revert "add count for range check" This reverts commit 5252444dfeaf41e7c336648ad92c4736f48ead9d. * Revert "range check imm limbs" This reverts commit 2e2937536069ae66849fdf7bba9ea509065d17fe. * fix unconstrained imm limbs * fix local_rs2_as test * fix lint * Update extensions/rv32im/circuit/src/base_alu/tests.rs --------- Co-authored-by: Jonathan Wang <[email protected]> * fix: fixed SHA2 subair trace generation and the testing (#28) * fix: loadstore sign of immediate (#4) * [fix] Fix P256 `GENERATOR` and `double_impl` (#2) * fix p256-generator * add host tests for ecc * fix: loadstore sign of immediate * fix: prints and test * fix: load_sign_extend tests * Update docs/specs/ISA.md * clarify notation and sign extension in ISA spec * fix reveal transpiler spec --------- Co-authored-by: Manh Dinh <[email protected]> Co-authored-by: Jonathan Wang <[email protected]> * fix transpiler * fix loadstore adapter * fix store transpiler * fix tests * add e2e test * fix docs * fix: jalr imm_sign (#30) * optimize record struct packing * chore: use from_bool * chore: derive_more feature in bench * fix bench * fix --------- Co-authored-by: Xinding Wei <[email protected]> Co-authored-by: Jonathan Wang <[email protected]> Co-authored-by: Golovanov399 <[email protected]> Co-authored-by: Avaneesh-axiom <[email protected]> Co-authored-by: Arayi Khalatyan <[email protected]>
spec: https://docs.google.com/document/d/1ajsBRZ6O5QRD5CgqlVfnc2c-tWh3gcUdbLH0KKE-3Js/edit