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    • CF_SRAM_1024x32

      Public
      Verilog
      1000Updated Dec 16, 2025Dec 16, 2025
    • caravel_user_project

      Public template
      Verilog
      910554Updated Dec 14, 2025Dec 14, 2025
    • Python
      02400Updated Dec 14, 2025Dec 14, 2025
    • ipm

      Public
      Python
      3471Updated Dec 10, 2025Dec 10, 2025
    • Commercial 16384x32 SRAM (64KB) - Wishbone compliant memory macro
      Verilog
      0000Updated Dec 9, 2025Dec 9, 2025
    • 32KB SRAM macro (8192 words × 32 bits) built from 8 × 1024x32 SRAM macros with Wishbone B4 interface
      Verilog
      0000Updated Dec 8, 2025Dec 8, 2025
    • Tiny Tapeout SKY 25b shuttle using sky130A PDK on ChipFoundry CC2511 MPW
      Verilog
      10000Updated Dec 6, 2025Dec 6, 2025
    • Verilog
      0000Updated Dec 6, 2025Dec 6, 2025
    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      Python
      72325900Updated Dec 2, 2025Dec 2, 2025
    • Python
      2000Updated Nov 22, 2025Nov 22, 2025
    • volare

      Public
      Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
      Python
      167467Updated Nov 19, 2025Nov 19, 2025
    • Verilog
      1201Updated Nov 19, 2025Nov 19, 2025
    • Tcl
      0001Updated Nov 19, 2025Nov 19, 2025
    • This project demonstrates the straightforward integration of a commercial Neuromorphic_X1_32x32 within the user_project_wrapper using the IPM (IP Manager) tool.
      Verilog
      5001Updated Nov 19, 2025Nov 19, 2025
    • Verilog
      0201Updated Nov 19, 2025Nov 19, 2025
    • Verilog
      2062Updated Nov 19, 2025Nov 19, 2025
    • openframe_user_project

      Public template
      Verilog
      4401Updated Nov 19, 2025Nov 19, 2025
    • nix-eda

      Public
      Nix derivations for EDA tools
      Nix
      81120Updated Nov 19, 2025Nov 19, 2025
    • The continuation of OpenLane 2, maintained under the FOSSi Foundation as "LibreLane." This repository primarily stores tags and and patches specific to ChipFoundry.
      Python
      43000Updated Nov 12, 2025Nov 12, 2025
    • Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
      Verilog
      147000Updated Nov 11, 2025Nov 11, 2025
    • chipdiscover-wokwi-template

      Public template
      Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Wokwi Projects
      Verilog
      20001Updated Nov 11, 2025Nov 11, 2025
    • Tiny Tapeout GDS Action (using OpenLane)
      22000Updated Nov 11, 2025Nov 11, 2025
    • tools used by project repos to test configuration, generate OpenLane run summaries and documentation
      Python
      23000Updated Nov 11, 2025Nov 11, 2025
    • Verilog
      1000Updated Nov 3, 2025Nov 3, 2025
    • Verilog
      1000Updated Oct 28, 2025Oct 28, 2025
    • caravel-sim-infrastructure

      Public
      HTML
      1046Updated Oct 21, 2025Oct 21, 2025
    • CF_TMR32

      Public
      Verilog
      1025Updated Oct 20, 2025Oct 20, 2025
    • CF_I2S

      Public
      Verilog
      0062Updated Oct 7, 2025Oct 7, 2025
    • CF_I2C

      Public
      Verilog
      0064Updated Oct 5, 2025Oct 5, 2025
    • frigate_user_project

      Public template
      Verilog
      0101Updated Oct 2, 2025Oct 2, 2025