[AVR] Cherry pick llvm#85277 #171
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LDDRdPtrQ was marked as `earlyclobber`, which doesn't play well with GreedyRA (which can generate this instruction through `loadRegFromStackSlot()`). This seems to be the same case as: https://github.com/llvm/llvm-project/blob/a99b912c9b74f6ef91786b4dfbc25160c27d3b41/llvm/lib/Target/AVR/AVRInstrInfo.td#L1421 Closes llvm#81911.
Patryk27
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Can you propose this for upstream backport to |
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Sure, sure: llvm#85422. |
Author
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Oki, got backported! |
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Thanks! We'll pick this patch up when merging the LLVM 18.1.2 release which will be tagged later today. I'll go ahead and close this PR... |
vext01
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Jun 5, 2024
Allow loads and stores with align >= the size of the data.
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Cherry pick llvm#85277, to fix Rahix/avr-hal#505 🙂