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c66d0b0
[libc++] Recategorize additional instantiations in the dylib as avail…
philnik777 Sep 14, 2023
185e16d
[mlir][bazel] Disable test added in https://github.com/llvm/llvm-proj…
chsigg Oct 6, 2023
5d8fb47
[InstCombine] Fold comparison of adding two z/sext booleans (#67895)
elhewaty Oct 6, 2023
0d7947b
[libc++] Implement P2614R2 (Deprecate numeric_limits::has_denorm)
philnik777 Sep 25, 2023
ff843c0
[libc++] Bump the clang version the clang-tidy checks are based on (#…
philnik777 Oct 6, 2023
0fcaca2
[mlir][bufferization] `MaterializeInDestinationOp`: Support memref de…
matthias-springer Oct 6, 2023
4e888e2
[MLIR] NFC. Fix clang-tidy warnings in Affine Utils
bondhugula Oct 6, 2023
b935882
Revert "[libc++] Remove UB in list, forward_list and __hash_table"
krasimirgg Oct 6, 2023
488a62f
[lld][ELF][AVR] Add range check for R_AVR_13_PCREL (#67636)
benshi001 Oct 6, 2023
a233a49
[lldb][DWARFASTParserClang][NFC] Fix comment regarding static data me…
Michael137 Oct 6, 2023
6a2071c
[mlir][transform] Allow passing various library files to interpreter.…
ingomueller-net Oct 6, 2023
3bae69e
[VectorCombine][X86] Add additional length changing foldBitcastShuf t…
RKSimon Oct 6, 2023
94795a3
[VectorCombine] foldBitcastShuf - add support for length changing shu…
RKSimon Oct 6, 2023
a16f646
[TTI] improveShuffleKindFromMask - detect SK_ExtractSubvector pattern…
RKSimon Oct 6, 2023
e13bed4
[PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP
d-smirnov Oct 6, 2023
ff48816
[AArch64][SME] Tile slices to lazy-save/restore should be RDSVL. (#68…
sdesmalen-arm Oct 6, 2023
46518a1
Revert "Revert "Fixes and closes #53952. Setting the ASTHasCompilerEr…
AaronBallman Oct 6, 2023
99e6ef3
[clang][NFC] Add missing placement-new after Allocate() calls (#68382)
Endilll Oct 6, 2023
4e311ea
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/6…
chsigg Oct 6, 2023
03bdfcc
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/6…
chsigg Oct 6, 2023
7e77f19
[TTI] Fix -Wsign-compare in BasicTTIImpl.h (NFC)
DamonFool Oct 6, 2023
ef8c26b
[mlir][Transform] Provide a minimal set of utils that allow implement…
nicolasvasilache Oct 6, 2023
32a9c09
[clang][CodeGen] Regenerate tests checks after 94795a37e892cfedb570c7…
RKSimon Oct 6, 2023
b9edf6d
[InstCombine] Add additional pre-commit tests for #67915. NFC.
dtcxzyw Oct 6, 2023
1cd14ad
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/e…
chsigg Oct 6, 2023
0e099fa
[AArch64][SME] NFC: use update_test_checks.py for sme-pstate(sm|za)-a…
sdesmalen-arm Oct 6, 2023
b3b3336
[InstCombine] Simplify the pattern `a ne/eq (zext/sext (a ne/eq c))` …
dtcxzyw Oct 6, 2023
ccf68ab
Revert "MachineSink: Fix sinking VGPR def out of a divergent loop"
petar-avramovic Sep 21, 2023
2d7fe90
AMDGPU: Add test for temporal divergence introduced by machine-sink
petar-avramovic Sep 21, 2023
2fa7d65
AMDGPU: Fix temporal divergence introduced by machine-sink (#67456)
petar-avramovic Oct 4, 2023
79c33d2
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/e…
chsigg Oct 6, 2023
48ee6bf
[mlir] Fix -Wunused-function in TransformInterpreterPassBase.cpp (NFC)
DamonFool Oct 6, 2023
22f81b4
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/e…
chsigg Oct 6, 2023
4cb6c1c
[libc] Enable missing memory tests on the GPU (#68111)
jhuber6 Oct 6, 2023
469b9cb
[mlir][VectorOps] Don't fold extract chains that include dynamic indi…
MacDue Oct 6, 2023
0a2aaab
[SPIRV] Implement log10 for logical SPIR-V (#66921)
sudonatalie Oct 6, 2023
d066300
[flang] Update instructions for a standalone flang build (#68361)
psteinfeld Oct 6, 2023
e18dca2
[IndVars] Add test for #68260 (NFC)
nikic Oct 6, 2023
529ad40
[PowerPC] Fix missing kill flag update for XVCVDPSP transformations (…
lei137 Oct 6, 2023
21030b9
[lldb][Docs] Add section on using QEMU without bridge networking
DavidSpickett Oct 6, 2023
2a1f1b5
[OpenMP][OpenMPIRBuilder] Move copyInput to a passed in lambda functi…
agozillon Oct 6, 2023
29a1567
[DWARFLinker] Release input DWARF after object has been linked (#68376)
JDevlieghere Oct 6, 2023
dd81c6a
[llvm][Docs][llvm-cov] Correct list of export options
DavidSpickett Oct 6, 2023
9d11ec7
[GitHub] Add myself to CODEOWNERS for LLDB (NFC)
JDevlieghere Oct 6, 2023
07f7f1c
Fix typo "x84_64" (#68419)
CaseyCarter Oct 6, 2023
f1b2dd2
[AArch64][BTI] Prevent Machine Scheduler from moving branch targets (…
atrosinenko Oct 6, 2023
d579a1a
[lldb[test] TestCppUnionStaticMembers.py: XFAIL assertions on windows…
Michael137 Oct 6, 2023
1556ddf
[flang][openacc] Do not generate duplicate routine op (#68348)
clementval Oct 6, 2023
6d6b395
[DebugInfo][SelectionDAG] Add debug info salvaging for TRUNC nodes
Sep 20, 2023
ffdae1a
[RISCV] Add autogen header to autogen test [nfc]
preames Oct 6, 2023
2c0b6f2
[AArch64][SME] Add remarks to flag lazy ZA saves, and SMSTART/SMSTOP …
jroelofs Oct 6, 2023
092ef55
[AArch64] Fix for misched-branch-targets.mir test
atrosinenko Oct 6, 2023
c91d3b0
[mlir][vector] Constrain patterns: vector.contract -> vector.outerpro…
banach-space Oct 6, 2023
98b114d
[InstCombine] Retain exact instruction name for some cases in Simplif…
topperc Oct 6, 2023
014912a
[MLIR][Presburger] Fix reduce bug in Fraction class and add tests (#6…
Abhinav271828 Oct 6, 2023
e9fa188
[SelectionDAG] Fix an unused variable warning
kazutakahirata Oct 6, 2023
8624075
[RISCV] Strip W suffix from ADDIW (#68425)
preames Oct 6, 2023
70368ea
[RISCV] Support VLS for VCIX (#67289)
4vtomat Oct 6, 2023
8f378ff
[lldb] Expose SBPlatform::GetAllProcesses to the SB API (#68378)
JDevlieghere Oct 6, 2023
f3c477a
[gn build] Port 8f378ff7a0a3
llvmgnsyncbot Oct 6, 2023
7f9a50f
[RISCV][GISel] Select G_SELECT (#67614)
nitinjohnraj Oct 6, 2023
a4d51e5
[compiler-rt] Allow Fuchsia to use 64-bit allocator for RISCV (#68343)
PiJoules Oct 6, 2023
0abaf3c
Revert "[RISCV][CostModel] VPIntrinsics have same cost as their non-v…
stellaraccident Oct 6, 2023
0a7bf3a
[CodeLayout] Faster basic block reordering, ext-tsp (#68275)
spupyrev Oct 6, 2023
5b39d8d
Revert "[CodeLayout] Faster basic block reordering, ext-tsp (#68275)"
Oct 6, 2023
e2a37cd
[StatepointLowering] Precommit test for #68439
zero9178 Oct 6, 2023
4a16b51
Make -frewrite-includes put an endif at the end of the included text …
pogo59 Oct 6, 2023
0dfb5da
[clang][modules] Remove preloaded SLocEntries from PCM files (#66962)
jansvoboda11 Oct 6, 2023
9500616
[NFC] Change a reference member to pointer
pogo59 Sep 27, 2023
71d83bb
Add -fkeep-system-includes modifier for -E
pogo59 Sep 28, 2023
5009d24
[Basic] Fix a warning
kazutakahirata Oct 6, 2023
7050ff4
[mlir] Fix `lower_unpack` when dynamic dimensions are involved (#68423)
qcolombet Oct 6, 2023
f045f2c
[AArch64][SME] Fix generating incorrect TBZ when lowering lazy save. …
aemerson Oct 6, 2023
d3af653
[mlir][sparse] introduce MapRef, unify conversion/codegen for reader …
aartbik Oct 6, 2023
cd0a824
add support for riscv64
alexfanqi Oct 6, 2023
ce8ed00
Revert Wframe-larger-than to 530
hiraditya Oct 6, 2023
4c94aff
[ADT] Add more ArrayRef <-> StringRef conversion functions
cachemeifyoucan Oct 4, 2023
d07c3cf
[Support] Introduce ThreadSafeAllocator
cachemeifyoucan Oct 5, 2023
5d2a710
[ADT] Introduce LazyAtomicPointer
cachemeifyoucan Oct 5, 2023
a9138cd
[libc++] Optimize ranges::count for __bit_iterators
philnik777 Oct 6, 2023
aade746
[libc++][PSTL] Overhaul exceptions handling
philnik777 Oct 6, 2023
daca972
[clang-tidy][libc] Fix namespace check with macro (#68134)
michaelrj-google Oct 6, 2023
0637440
[mlir][sparse] introduce a pass to stage complex sparse operations in…
PeimingLiu Oct 6, 2023
b53ff43
[scudo] Improve the message of region exhaustion (#68444)
ChiaHungDuan Oct 6, 2023
767dcc5
[llvm][Support] fix convertToSnakeFromCamelCase (#68375)
makslevental Oct 6, 2023
8eff5e4
Add '-p' argument to mkdir in test so that it does not give an error …
dyung Oct 6, 2023
537344f
[clang][modules] Move `SLocEntry` search into `ASTReader` (#66966)
jansvoboda11 Oct 6, 2023
531233d
Revert "add support for riscv64"
zeroomega Oct 6, 2023
7510f32
[MachineSink] Fix crash due to use-after-free in a MachineInstr* cache.
aemerson Oct 6, 2023
28e8ade
[clang] Fix build after 537344fc
jansvoboda11 Oct 6, 2023
5619e1b
Fix non-determinism in debuginfo (#68332)
ilovepi Oct 6, 2023
285ab3e
[clang] Fix tests build after 537344fc
jansvoboda11 Oct 6, 2023
9c2bdb6
[gn build] Port 5d2a7101b72a
llvmgnsyncbot Oct 6, 2023
8e47571
[gn build] Port aade74675c15
llvmgnsyncbot Oct 6, 2023
2cbdeb7
[gn build] Port d07c3cf66716
llvmgnsyncbot Oct 6, 2023
7850225
[DWARF] Change to consistently print out abbrev code in .debug_names …
ayermolo Oct 6, 2023
e29a253
[mlir][tosa][linalg] Apply direct tosa -> linalg Conv2D lowering (#68…
FranklandJack Oct 7, 2023
a9e9727
[libcxxabi] Add missing include statement.
cmtice Oct 6, 2023
6afceba
[AMDGPU][IGLP] SingleWaveOpt: Cache DSW Counters from PreRA (#67759)
jrbyrnes Oct 7, 2023
869d168
[clang][ASTImporter] Fix crash when import `VarTemplateDecl` in recor…
jcsxky Oct 7, 2023
fa23a23
[libc] Fix linking of AMDGPU device runtime control constants for mat…
jhuber6 Oct 7, 2023
8abb2ac
Revert "Re-apply "[AArch64] Enable "sink-and-fold" in MachineSink by …
cmtice Oct 7, 2023
be383de
Fix machine-sink-cache-invalidation post - 8abb2ace8
mtrofin Oct 7, 2023
e6e9beb
[mlir][tools] Introduce tblgen-to-irdl tool (#66865)
Groverkss Oct 7, 2023
c654193
[clang][Lex][NFC] Make some local variables const
tbaederr Oct 5, 2023
ee9f96b
[RISCV][GISel] Add FPR register bank.
topperc Oct 7, 2023
859f2d0
Revert "Reapply "[clang analysis][thread-safety] Handle return-by-ref…
cmtice Oct 7, 2023
3a3b84b
[clang] remove ClassScopeFunctionSpecializationDecl (#66636)
sdkrystian Oct 7, 2023
3a158cc
[clang] Fix -Wreorder-ctor of DependentFunctionTemplateSpecialization…
DamonFool Oct 7, 2023
2fc5649
[bazel] Add missing dependency for 5d2a7101b72a8cae8c4c1f7a11ede7f656…
d0k Oct 7, 2023
807e745
LangRef: add missing punctuation (#68471)
RalfJung Oct 7, 2023
7b93611
[BOLT][RISCV] Fix reloc-tls tests
mtvec Oct 7, 2023
116a1ae
Fix Clang Sphinx build
AaronBallman Oct 7, 2023
2bed2a7
[clang][Interp] Emit dummy values for unknown C variables (#66749)
tbaederr Oct 7, 2023
c226d6c
[Documentation][NFC] Remove invalid language specifiers in markdown c…
cor3ntin Oct 7, 2023
ce093d5
[clang][Intepr] Fix the build
tbaederr Oct 7, 2023
635eb5f
[clang][NFC] Typo fix in PPC.cpp
hubert-reinterpretcast Oct 7, 2023
8ee38f3
[mlir][bufferization] Follow up for #68074 (#68488)
matthias-springer Oct 7, 2023
45636ec
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
topperc Oct 7, 2023
c4f32b4
[AArch64] Tests for postinc scheduling write operands. NFC
davemgreen Oct 7, 2023
bae41ff
[BOLT] Fix long jump negative offset issue. (#67132)
qijitao Oct 7, 2023
dae91f5
[VPlan] Avoid VPTransformState::reset in fixReduction (NFCI).
fhahn Oct 7, 2023
701d804
[clang][Modules] `checkModuleIsAvailable` should use a const & parame…
davidstone Oct 8, 2023
76fc871
[RISCV] Support fptoi like ops for fp16 vectors input when only have …
jacquesguan Oct 8, 2023
11caef0
[AArch64][GlobalISel][NFC] Re-generate a test.
aemerson Oct 8, 2023
18622fc
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
wangpc-pp Oct 8, 2023
b8f70fe
[llvm] Remove "using support::endianness;" (NFC)
kazutakahirata Oct 8, 2023
32f7197
[VP] Use the interface of 'getFunctionalIntrinsicID' to get the non-p…
LiqinWeng Oct 8, 2023
8763343
[mlir][bufferization] Update empty_tensor_elimination transform op (#…
matthias-springer Oct 8, 2023
7cc1bfa
[clang-tidy][modernize-return-braced-init-list]fix false-positives (#…
HerrCai0907 Oct 8, 2023
7cfe32d
[Driver] Hook up Haiku ARM support (#67222)
brad0 Oct 9, 2023
c98bf1e
[Sparc] Replace CMP instructions with InstAlias (NFCI) (#66859)
s-barannikov Oct 9, 2023
6480fe2
[llvm] Drop unaligned from calls to llvm::support::endian::{read,writ…
kazutakahirata Oct 9, 2023
cf5639d
[lldb][Docs] Fix typo in debugging lldb doc
DavidSpickett Oct 9, 2023
f47914a
[lldb][Docs] Use RST link format in IntelPT doc
DavidSpickett Oct 9, 2023
87b2682
[flang][hlfir] use fir.type_info to skip runtime call if nofinal is s…
jeanPerier Oct 9, 2023
8868431
[flang] Set func.func arg attributes for procedure designators (#68420)
jeanPerier Oct 9, 2023
cb550c1
Update MLIR conversion to LLVMFunc to account better for properties (…
joker-eph Oct 9, 2023
d7b18d5
Use llvm::endianness{,::little,::native} (NFC)
kazutakahirata Oct 9, 2023
8b73265
[SPIRV] Fix SPV_KHR_expect_assume support (#67793)
pmatos Oct 9, 2023
42c564d
[clang-format][NFC] Make InsertNewlineAtEOF a little more efficient
owenca Oct 9, 2023
8d07d9f
[AArch64][SME] Zero reserved bytes when allocating a new TPIDR2 objec…
kmclaughlin-arm Oct 9, 2023
7bbfd2a
[mlir][ArmSVE] Restructure sources to match ArmSME dialect (NFC) (#68…
MacDue Oct 9, 2023
e0809bd
Fix Wparentheses warning. NFC.
RKSimon Oct 9, 2023
29b2082
Fix Wunused-variable warning. NFC.
RKSimon Oct 9, 2023
acf0717
[Docs] Fix GEP type in example (#68533)
mariusz-sikora-at-amd Oct 9, 2023
072675f
[DAG] foldSelectOfBinops - correctly handle select of binops where Re…
RKSimon Oct 9, 2023
3273ea4
[LV] Cache call vectorization decisions (#66521)
huntergr-arm Oct 9, 2023
bea3967
[VectorCombine] Rename foldBitcastShuf -> foldBitcastShuffle. NFC.
RKSimon Oct 9, 2023
573a083
[DAG] Remove unused variable 'VT' in DAGCombiner.cpp (NFC)
DamonFool Oct 9, 2023
648046d
[mlir][bazel] Fix after 7bbfd2a
JoelWee Oct 9, 2023
2501ae5
[CodeGen] Really renumber slot indexes before register allocation (#6…
jayfoad Oct 9, 2023
df116d1
[MemCpyOpt] Fix the invalid code modification for GEP (#68479)
kaiyan96 Oct 9, 2023
7b3bbd8
Revert "[CodeGen] Really renumber slot indexes before register alloca…
jayfoad Oct 9, 2023
71a8d2e
[MachineLICM] Relax overlay conservative PHI check (#67186)
Oct 9, 2023
6afbc09
[NFS][CodeMoverUtils] Add comment saying not ready for production usa…
dtemirbulatov Oct 9, 2023
2856e72
[analyzer][NFC] Remove outdated FIXME comment (#68211)
NagyDonat Oct 9, 2023
60f7aa1
[clang-tidy] add namespace qualifier NFC (#68579)
metaflow Oct 9, 2023
111c7c1
[VP] IR expansion for bitreverse/bswap (#68504)
LiqinWeng Oct 9, 2023
8840da2
Reapply [Verifier] Sanity check alloca size against DILocalVariable f…
nikic Aug 24, 2023
2600aaa
Revert "[MachineLICM] Relax overlay conservative PHI check (#67186)" …
Oct 9, 2023
708999e
[IndVars] Add test for phi select exit value with large BTC (NFC)
nikic Oct 9, 2023
a56071f
[SCEV] Don't require positive BTC when non-zero is sufficient
nikic Oct 9, 2023
bcf172e
[libc++] LWG 3821 uses_allocator_construction_args should have overlo…
huixie90 Oct 9, 2023
85feb93
[OpenMP] Fix setting visibility on declare target variables
jhuber6 Oct 9, 2023
171a3a6
[VP][NFC] Add 32-bit test for VP (#68582)
LiqinWeng Oct 9, 2023
9050b27
[OpenMPIRBuilder] Remove wrapper function in `createTask`, `createTea…
shraiysh Oct 9, 2023
e01c867
[mlir][vector] Restore assert and fix typos (#68581)
banach-space Oct 9, 2023
e7b2855
[ConstantFold] Avoid some uses of ConstantExpr::getSExt() (NFC)
nikic Oct 9, 2023
462d583
[GlobalISel] Add support for *_fpmode intrinsics
spavloff Oct 9, 2023
2a2b426
[Sink] Fix bugs of sinking unreachable BB from phi (#68576)
XChy Oct 9, 2023
1c3fdb3
Revert "[SCEV] Don't invalidate past dependency-breaking instructions"
nikic Oct 9, 2023
f9bd62f
[clang-tidy] Improve `ExceptionSpecAnalyzer`s handling of conditional…
AMS21 Oct 9, 2023
df8e0d0
[AArch64][LoopVectorize] Use upper bound trip count instead of the co…
Oct 9, 2023
e44cfe0
[InstCombine] Precommit test for PR68465
vfdff Oct 8, 2023
ea86fb8
[InstCombine] Fold zext-of-icmp with no shift (#68503)
vfdff Oct 9, 2023
b7188d2
[mlir][sparse] replace specialized buffer setup with util code (#68461)
aartbik Oct 9, 2023
414709e
[mlir][tosa] Add verifier for `ArgMax` operator (#68410)
GeorgeARM Oct 9, 2023
a942f7c
[mlir][sparse] move variable into assert to avoid 'unused' error (#68…
aartbik Oct 9, 2023
e85cdb9
[flang][openacc] Support allocatable and pointer array in private rec…
clementval Oct 9, 2023
2615de5
Revert "[flang][openacc] Support allocatable and pointer array in pri…
clementval Oct 9, 2023
a968bec
Revert "[mlir][tools] Introduce tblgen-to-irdl tool (#66865)"
thurstond Oct 9, 2023
470b652
[flang][openacc] Support allocatable and pointer array in private recipe
clementval Oct 5, 2023
6e8ffab
[mlir][nvvm] Introduce `elect.sync` Op (#68323)
grypp Oct 9, 2023
303e020
[FrontEnd] Fix a warning
kazutakahirata Oct 9, 2023
2e82696
[lldb][NFCI] Remove use of ConstString from FilterRule in StructuredD…
bulbazord Oct 9, 2023
86b44f3
[flang][openacc] Added acc::RecipeInterface for getting alloca insert…
vzakhari Oct 9, 2023
38c31d7
[clang-format][NFC] Annotate more r_braces
HazardyKnusperkeks Oct 9, 2023
b7abab2
Annotate enum r brace
HazardyKnusperkeks Oct 9, 2023
6668d14
[mlir][arith] Canonicalization patterns for `arith.select` (#67809)
peterbell10 Oct 9, 2023
08b20d8
[RISCV] Generaize reduction tree matching to fp sum reductions (#68599)
preames Oct 9, 2023
67b675e
Revert "[Clang] Implement the 'counted_by' attribute" (#68603)
alexfh Oct 9, 2023
cbafb6f
[NVPTX] Improve lowering of v4i8 (#67866)
Artem-B Oct 9, 2023
65a576e
[X86] Add tests for incorrectly optimizing out shuffle used in `movms…
goldsteinn Oct 6, 2023
1684c65
[X86] Fix logic for optimizing movmsk(bitcast(shuffle(x))); PR67287
goldsteinn Oct 8, 2023
7a73da4
[clang-tidy] Add support for optional parameters in config.
felix642 Oct 9, 2023
b9c6737
[scudo] Make local cache be agnostic to the type of node in freelist …
ChiaHungDuan Oct 9, 2023
5e3f43e
[libcxx] [test] Quote the python executable in the executor (#68208)
mstorsjo Oct 9, 2023
3548b79
[LLD] [MinGW] Handle the --dll option (#68575)
mstorsjo Oct 9, 2023
37432c1
Revert "[compiler-rt] Allow Fuchsia to use 64-bit allocator for RISCV…
PiJoules Oct 9, 2023
540a1a6
[clang-cl] Document behavior difference of strict aliasing in clang-c…
huihzhang Oct 9, 2023
8dd9615
Revert "[scudo] Make local cache be agnostic to the type of node in f…
ChiaHungDuan Oct 9, 2023
27c6d55
[mlir][python] generate value builders (#68308)
makslevental Oct 9, 2023
9827467
[Debuginfod] Add \n to llvm-debuginfod-find error
mysterymath Oct 9, 2023
c2ae16f
[VectorCombine]Fix a crash during long vector analysis.
alexey-bataev Oct 9, 2023
561fbe4
[flang][hlfir] address char_convert issues as mentioned in #64315 (#6…
cabreraam Oct 9, 2023
07d2e90
Remove LLDB introspection entrypoints from the shim (#68450)
rsundahl Oct 9, 2023
d5622de
[mlir][sparse] rename map utility (#68611)
aartbik Oct 9, 2023
ab6334d
[mlir][sparse] add expanded size to API (#68614)
aartbik Oct 9, 2023
bc34a83
[ASan][Windows] Fix rip-relative instruction replacement (#68432)
strega-nil Oct 9, 2023
eb60143
[llvm][objdump] Remove support for printing the embedded Bitcode sect…
ributzka Oct 9, 2023
3684f6a
[OpenACC][Bazel] Added OpenACCOpsInterfaces to BUILD.bazel file (#68639)
bviyer Oct 9, 2023
115b6a3
[Sanitizer][Docs] Improve docs on building Asan (#68636)
boomanaiden154 Oct 9, 2023
24b0c43
Reapply "[scudo] Make local cache be agnostic to the type of node in …
ChiaHungDuan Oct 9, 2023
6828194
[Sanitizer][Docs] Reformat CMake invocation in docs
boomanaiden154 Oct 9, 2023
f8148e4
[Github] Add PR author name to subscription email (#68440)
boomanaiden154 Oct 9, 2023
d4feffb
[gn] port 24b0c43c9916
nico Oct 9, 2023
f92309a
[flang][runtime] Workaround cuda-11.8 compilation issue. (#68459)
vzakhari Oct 9, 2023
ac0dda8
[lldb] add stop-at-user-entry option to process launch (#67019)
junior-jl Oct 9, 2023
14d0cd6
[mlir][sparse] Fix errors in doc and tests (#68641)
yinying-lisa-li Oct 10, 2023
c8b5f4c
[flang][openacc] Support array with dynamic extent in private recipe …
clementval Oct 10, 2023
3d0ca2c
[mlir][bufferization] Allow cyclic function graphs without tensors (#…
matthias-springer Oct 10, 2023
9d34c05
[mlir][bufferization][NFC] Simplify `bufferizeOp` function signature …
matthias-springer Oct 10, 2023
48a73bc
[mlir][sparse] Extract `StorageSpecifierToLLVMPass` from bufferizatio…
matthias-springer Oct 10, 2023
efb11c4
Support big endian in llvm-symbolizer's data location dwarf info pars…
Oct 10, 2023
057ec76
[X86][NFC]Update test cases after D159250 (#68517)
XinWang10 Oct 10, 2023
b5dffd4
[C++20] [Modules] Don't emit function bodies which is noinline and av…
ChuanqiXu9 Oct 10, 2023
feea5db
[X86] Support EGPR (R16-R31) for APX (#67702)
KanRobert Oct 10, 2023
7645df6
[RISCV] Simplify PatSetCC_m and PatFprFprDynFrm_m (#68562)
Oct 10, 2023
9ab732f
[MLIR][TOSA] Add tosa.slice operation conversion failure scenario (#6…
LiqinWeng Oct 10, 2023
80815df
[mlir] remove some GCC warning #68409 (#68528)
lipracer Oct 10, 2023
0d0f219
[JITLink] Allow pre-existing eh-frame CIE edges on FDEs.
lhames Oct 10, 2023
4790578
[mlir] Make overloads of SymbolTable::replaceAllSymbolUses consistent…
ingomueller-net Oct 10, 2023
7926744
-fsanitize=alignment: check memcpy/memmove arguments (#67766)
MaskRay Oct 10, 2023
79f87be
[clang] Fix several issues in the generated AttrHasAttributeImpl.inc
s-barannikov Sep 2, 2023
5fa5ffe
[Clang] Fix missing diagnostic for non-standard layout type in `offse…
kasuga-fj Oct 10, 2023
909087c
Replace hard coded numbers from 462d583 with regex so the test passes…
dyung Oct 10, 2023
d37056c
[MLIR][TOSA] Remove failed test cases (#68664)
LiqinWeng Oct 10, 2023
a2b8c49
[clang] [MinGW] Explicitly always pass the -fno-use-init-array (#68571)
mstorsjo Oct 10, 2023
f74e9f8
[Aarch64] Materialize immediates with 64-bit ORR + EOR if shorter (#6…
dougallj Oct 10, 2023
e46822e
[gitattributes] Don't mark all llvm-rc test Inputs as binary (#68583)
mstorsjo Oct 10, 2023
aa5158c
[AMDGPU] Use absolute relocations when compiling for AMDPAL and Mesa3…
tsymalla Oct 10, 2023
19d1da5
[clang]Avoid diagnose invalid consteval call for invalid function dec…
HerrCai0907 Oct 10, 2023
f5031c6
[AArch64] Fix postinc operands for Cortex-A510 scheduling
davemgreen Oct 10, 2023
3542dd8
[clang][Interp][NFC] Move int128 tests to their own file
tbaederr Oct 10, 2023
8185794
[LVI][CVP] Treat undef like a full range (#68190)
dianqk Oct 10, 2023
962a049
[bazel] fix build for 479057887fbc8bfef17c86694f78496c54550f21
metaflow Oct 10, 2023
3d70ba6
[mlir][ArmSVE] Add convert.from/to.svbool intrinsics (#68418)
MacDue Oct 10, 2023
141ca54
[bazel] fix build for 479057887fbc8bfef17c86694f78496c54550f21
metaflow Oct 10, 2023
6b3d4b8
[AMDGPU] Add encoding/decoding support for non-result-returning ATOMI…
stepthomas Oct 4, 2023
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30 changes: 30 additions & 0 deletions .github/CODEOWNERS
Original file line number Diff line number Diff line change
@@ -1,4 +1,34 @@
# This file lists reviewers that are auto-assigned when a pull request modifies
# certain files or directories. If you add yourself to this file, you commit to
# reviewing a large fraction of pull requests in the relevant area.
#
# The GitHub "code owners" mechanism is used exclusively to auto-assign
# reviewers and does not carry significance beyond that. It is not necessary
# to receive an approval from a "code owner" in particular -- any LLVM project
# member can approve pull requests.
#
# Note that GitHub's concept of "code owner" is independent from LLVM's own
# "code owner" concept, they merely happen to share terminology. See
# https://llvm.org/docs/DeveloperPolicy.html#code-owners, as well as the
# CODE_OWNERS.txt files in the respective subproject directories.

/libcxx/ @llvm/reviewers-libcxx
/libcxxabi/ @llvm/reviewers-libcxxabi
/libunwind/ @llvm/reviewers-libunwind
/runtimes/ @llvm/reviewers-libcxx

/llvm/lib/Analysis/BasicAliasAnalysis.cpp @nikic
/llvm/lib/Analysis/InstructionSimplify.cpp @nikic
/llvm/lib/Analysis/LazyValueInfo.cpp @nikic
/llvm/lib/Analysis/ScalarEvolution.cpp @nikic
/llvm/lib/Analysis/ValueTracking.cpp @nikic
/llvm/lib/IR/ConstantRange.cpp @nikic
/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp @nikic
/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp @nikic
/llvm/lib/Transforms/InstCombine/ @nikic

/clang/test/CXX/drs/ @Endilll
/clang/www/cxx_dr_status.html @Endilll
/clang/www/make_cxx_dr_status @Endilll

/lldb/ @JDevlieghere
1 change: 1 addition & 0 deletions bolt/include/bolt/Core/MCPlus.h
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@ class MCAnnotation {
kTailCall, /// Tail call.
kConditionalTailCall, /// CTC.
kOffset, /// Offset in the function.
kLabel, /// MCSymbol pointing to this instruction.
kGeneric /// First generic annotation.
};

Expand Down
21 changes: 16 additions & 5 deletions bolt/include/bolt/Core/MCPlusBuilder.h
Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,7 @@ class MCPlusBuilder {
const MCInstrAnalysis *Analysis;
const MCInstrInfo *Info;
const MCRegisterInfo *RegInfo;
const MCSubtargetInfo *STI;

/// Map annotation name into an annotation index.
StringMap<uint64_t> AnnotationNameIndexMap;
Expand Down Expand Up @@ -331,8 +332,8 @@ class MCPlusBuilder {

public:
MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info,
const MCRegisterInfo *RegInfo)
: Analysis(Analysis), Info(Info), RegInfo(RegInfo) {
const MCRegisterInfo *RegInfo, const MCSubtargetInfo *STI)
: Analysis(Analysis), Info(Info), RegInfo(RegInfo), STI(STI) {
// Initialize the default annotation allocator with id 0
AnnotationAllocators.emplace(0, AnnotationAllocator());
MaxAllocatorId++;
Expand Down Expand Up @@ -1179,6 +1180,13 @@ class MCPlusBuilder {
/// Remove offset annotation.
bool clearOffset(MCInst &Inst);

/// Return the label of \p Inst, if available.
std::optional<MCSymbol *> getLabel(const MCInst &Inst) const;

/// Set the label of \p Inst. This label will be emitted right before \p Inst
/// is emitted to MCStreamer.
bool setLabel(MCInst &Inst, MCSymbol *Label);

/// Return MCSymbol that represents a target of this instruction at a given
/// operand number \p OpNum. If there's no symbol associated with
/// the operand - return nullptr.
Expand Down Expand Up @@ -2079,15 +2087,18 @@ class MCPlusBuilder {

MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *,
const MCInstrInfo *,
const MCRegisterInfo *);
const MCRegisterInfo *,
const MCSubtargetInfo *);

MCPlusBuilder *createAArch64MCPlusBuilder(const MCInstrAnalysis *,
const MCInstrInfo *,
const MCRegisterInfo *);
const MCRegisterInfo *,
const MCSubtargetInfo *);

MCPlusBuilder *createRISCVMCPlusBuilder(const MCInstrAnalysis *,
const MCInstrInfo *,
const MCRegisterInfo *);
const MCRegisterInfo *,
const MCSubtargetInfo *);

} // namespace bolt
} // namespace llvm
Expand Down
4 changes: 4 additions & 0 deletions bolt/include/bolt/Core/Relocation.h
Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,10 @@ struct Relocation {
/// Return true if relocation type is for thread local storage.
static bool isTLS(uint64_t Type);

/// Return true of relocation type is for referencing a specific instruction
/// (as opposed to a function, basic block, etc).
static bool isInstructionReference(uint64_t Type);

/// Return code for a NONE relocation
static uint64_t getNone();

Expand Down
3 changes: 2 additions & 1 deletion bolt/include/bolt/Rewrite/RewriteInstance.h
Original file line number Diff line number Diff line change
Expand Up @@ -584,7 +584,8 @@ class RewriteInstance {
MCPlusBuilder *createMCPlusBuilder(const Triple::ArchType Arch,
const MCInstrAnalysis *Analysis,
const MCInstrInfo *Info,
const MCRegisterInfo *RegInfo);
const MCRegisterInfo *RegInfo,
const MCSubtargetInfo *STI);

} // namespace bolt
} // namespace llvm
Expand Down
2 changes: 2 additions & 0 deletions bolt/lib/Core/BinaryContext.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1888,6 +1888,8 @@ void BinaryContext::printInstruction(raw_ostream &OS, const MCInst &Instruction,
}
if (std::optional<uint32_t> Offset = MIB->getOffset(Instruction))
OS << " # Offset: " << *Offset;
if (auto Label = MIB->getLabel(Instruction))
OS << " # Label: " << **Label;

MIB->printAnnotations(Instruction, OS);

Expand Down
3 changes: 3 additions & 0 deletions bolt/lib/Core/BinaryEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -498,6 +498,9 @@ void BinaryEmitter::emitFunctionBody(BinaryFunction &BF, FunctionFragment &FF,
BB->getLocSyms().emplace_back(Offset, LocSym);
}

if (auto Label = BC.MIB->getLabel(Instr))
Streamer.emitLabel(*Label);

Streamer.emitInstruction(Instr, *BC.STI);
LastIsPrefix = BC.MIB->isPrefix(Instr);
}
Expand Down
37 changes: 33 additions & 4 deletions bolt/lib/Core/BinaryFunction.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1173,6 +1173,13 @@ bool BinaryFunction::disassemble() {
// basic block.
Labels[0] = Ctx->createNamedTempSymbol("BB0");

// Map offsets in the function to a label that should always point to the
// corresponding instruction. This is used for labels that shouldn't point to
// the start of a basic block but always to a specific instruction. This is
// used, for example, on RISC-V where %pcrel_lo relocations point to the
// corresponding %pcrel_hi.
LabelsMapType InstructionLabels;

uint64_t Size = 0; // instruction size
for (uint64_t Offset = 0; Offset < getSize(); Offset += Size) {
MCInst Instruction;
Expand Down Expand Up @@ -1329,9 +1336,23 @@ bool BinaryFunction::disassemble() {
ItrE = Relocations.lower_bound(Offset + Size);
Itr != ItrE; ++Itr) {
const Relocation &Relocation = Itr->second;
MCSymbol *Symbol = Relocation.Symbol;

if (Relocation::isInstructionReference(Relocation.Type)) {
uint64_t RefOffset = Relocation.Value - getAddress();
LabelsMapType::iterator LI = InstructionLabels.find(RefOffset);

if (LI == InstructionLabels.end()) {
Symbol = BC.Ctx->createNamedTempSymbol();
InstructionLabels.emplace(RefOffset, Symbol);
} else {
Symbol = LI->second;
}
}

int64_t Value = Relocation.Value;
const bool Result = BC.MIB->replaceImmWithSymbolRef(
Instruction, Relocation.Symbol, Relocation.Addend, Ctx.get(), Value,
Instruction, Symbol, Relocation.Addend, Ctx.get(), Value,
Relocation.Type);
(void)Result;
assert(Result && "cannot replace immediate with relocation");
Expand Down Expand Up @@ -1366,6 +1387,13 @@ bool BinaryFunction::disassemble() {
addInstruction(Offset, std::move(Instruction));
}

for (auto [Offset, Label] : InstructionLabels) {
InstrMapType::iterator II = Instructions.find(Offset);
assert(II != Instructions.end() && "reference to non-existing instruction");

BC.MIB->setLabel(II->second, Label);
}

// Reset symbolizer for the disassembler.
BC.SymbolicDisAsm->setSymbolizer(nullptr);

Expand Down Expand Up @@ -1761,7 +1789,8 @@ bool BinaryFunction::postProcessIndirectBranches(
uint64_t LastJT = 0;
uint16_t LastJTIndexReg = BC.MIB->getNoRegister();
for (BinaryBasicBlock &BB : blocks()) {
for (MCInst &Instr : BB) {
for (BinaryBasicBlock::iterator II = BB.begin(); II != BB.end(); ++II) {
MCInst &Instr = *II;
if (!BC.MIB->isIndirectBranch(Instr))
continue;

Expand Down Expand Up @@ -1789,7 +1818,7 @@ bool BinaryFunction::postProcessIndirectBranches(
const MCExpr *DispExpr;
MCInst *PCRelBaseInstr;
IndirectBranchType Type = BC.MIB->analyzeIndirectBranch(
Instr, BB.begin(), BB.end(), PtrSize, MemLocInstr, BaseRegNum,
Instr, BB.begin(), II, PtrSize, MemLocInstr, BaseRegNum,
IndexRegNum, DispValue, DispExpr, PCRelBaseInstr);
if (Type != IndirectBranchType::UNKNOWN || MemLocInstr != nullptr)
continue;
Expand Down Expand Up @@ -4488,7 +4517,7 @@ void BinaryFunction::addRelocation(uint64_t Address, MCSymbol *Symbol,
uint64_t Offset = Address - getAddress();
LLVM_DEBUG(dbgs() << "BOLT-DEBUG: addRelocation in "
<< formatv("{0}@{1:x} against {2}\n", *this, Offset,
Symbol->getName()));
(Symbol ? Symbol->getName() : "<undef>")));
bool IsCI = BC.isAArch64() && isInConstantIsland(Address);
std::map<uint64_t, Relocation> &Rels =
IsCI ? Islands->Relocations : Relocations;
Expand Down
11 changes: 11 additions & 0 deletions bolt/lib/Core/MCPlusBuilder.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -268,6 +268,17 @@ bool MCPlusBuilder::clearOffset(MCInst &Inst) {
return true;
}

std::optional<MCSymbol *> MCPlusBuilder::getLabel(const MCInst &Inst) const {
if (auto Label = tryGetAnnotationAs<MCSymbol *>(Inst, MCAnnotation::kLabel))
return *Label;
return std::nullopt;
}

bool MCPlusBuilder::setLabel(MCInst &Inst, MCSymbol *Label) {
getOrCreateAnnotationAs<MCSymbol *>(Inst, MCAnnotation::kLabel) = Label;
return true;
}

bool MCPlusBuilder::hasAnnotation(const MCInst &Inst, unsigned Index) const {
const MCInst *AnnotationInst = getAnnotationInst(Inst);
if (!AnnotationInst)
Expand Down
39 changes: 39 additions & 0 deletions bolt/lib/Core/Relocation.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,13 @@
using namespace llvm;
using namespace bolt;

namespace ELFReserved {
enum {
R_RISCV_TPREL_I = 49,
R_RISCV_TPREL_S = 50,
};
} // namespace ELFReserved

Triple::ArchType Relocation::Arch;

static bool isSupportedX86(uint64_t Type) {
Expand Down Expand Up @@ -111,6 +118,13 @@ static bool isSupportedRISCV(uint64_t Type) {
case ELF::R_RISCV_LO12_I:
case ELF::R_RISCV_LO12_S:
case ELF::R_RISCV_64:
case ELF::R_RISCV_TLS_GOT_HI20:
case ELF::R_RISCV_TPREL_HI20:
case ELF::R_RISCV_TPREL_ADD:
case ELF::R_RISCV_TPREL_LO12_I:
case ELF::R_RISCV_TPREL_LO12_S:
case ELFReserved::R_RISCV_TPREL_I:
case ELFReserved::R_RISCV_TPREL_S:
return true;
}
}
Expand Down Expand Up @@ -214,6 +228,7 @@ static size_t getSizeForTypeRISCV(uint64_t Type) {
return 4;
case ELF::R_RISCV_64:
case ELF::R_RISCV_GOT_HI20:
case ELF::R_RISCV_TLS_GOT_HI20:
// See extractValueRISCV for why this is necessary.
return 8;
}
Expand Down Expand Up @@ -532,6 +547,7 @@ static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents,
case ELF::R_RISCV_BRANCH:
return extractBImmRISCV(Contents);
case ELF::R_RISCV_GOT_HI20:
case ELF::R_RISCV_TLS_GOT_HI20:
// We need to know the exact address of the GOT entry so we extract the
// value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the
// relocation for this since it simply refers to the object that is stored
Expand Down Expand Up @@ -600,6 +616,7 @@ static bool isGOTRISCV(uint64_t Type) {
default:
return false;
case ELF::R_RISCV_GOT_HI20:
case ELF::R_RISCV_TLS_GOT_HI20:
return true;
}
}
Expand Down Expand Up @@ -636,6 +653,14 @@ static bool isTLSRISCV(uint64_t Type) {
switch (Type) {
default:
return false;
case ELF::R_RISCV_TLS_GOT_HI20:
case ELF::R_RISCV_TPREL_HI20:
case ELF::R_RISCV_TPREL_ADD:
case ELF::R_RISCV_TPREL_LO12_I:
case ELF::R_RISCV_TPREL_LO12_S:
case ELFReserved::R_RISCV_TPREL_I:
case ELFReserved::R_RISCV_TPREL_S:
return true;
}
}

Expand Down Expand Up @@ -733,6 +758,7 @@ static bool isPCRelativeRISCV(uint64_t Type) {
case ELF::R_RISCV_RVC_JUMP:
case ELF::R_RISCV_RVC_BRANCH:
case ELF::R_RISCV_32_PCREL:
case ELF::R_RISCV_TLS_GOT_HI20:
return true;
}
}
Expand Down Expand Up @@ -832,6 +858,19 @@ bool Relocation::isTLS(uint64_t Type) {
return isTLSX86(Type);
}

bool Relocation::isInstructionReference(uint64_t Type) {
if (Arch != Triple::riscv64)
return false;

switch (Type) {
default:
return false;
case ELF::R_RISCV_PCREL_LO12_I:
case ELF::R_RISCV_PCREL_LO12_S:
return true;
}
}

uint64_t Relocation::getNone() {
if (Arch == Triple::aarch64)
return ELF::R_AARCH64_NONE;
Expand Down
5 changes: 5 additions & 0 deletions bolt/lib/Passes/BinaryPasses.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -575,6 +575,7 @@ bool CheckLargeFunctions::shouldOptimize(const BinaryFunction &BF) const {

void LowerAnnotations::runOnFunctions(BinaryContext &BC) {
std::vector<std::pair<MCInst *, uint32_t>> PreservedOffsetAnnotations;
std::vector<std::pair<MCInst *, MCSymbol *>> PreservedLabelAnnotations;

for (auto &It : BC.getBinaryFunctions()) {
BinaryFunction &BF = It.second;
Expand Down Expand Up @@ -609,6 +610,8 @@ void LowerAnnotations::runOnFunctions(BinaryContext &BC) {
if (BF.requiresAddressTranslation() && BC.MIB->getOffset(*II))
PreservedOffsetAnnotations.emplace_back(&(*II),
*BC.MIB->getOffset(*II));
if (auto Label = BC.MIB->getLabel(*II))
PreservedLabelAnnotations.emplace_back(&*II, *Label);
BC.MIB->stripAnnotations(*II);
}
}
Expand All @@ -625,6 +628,8 @@ void LowerAnnotations::runOnFunctions(BinaryContext &BC) {
// Reinsert preserved annotations we need during code emission.
for (const std::pair<MCInst *, uint32_t> &Item : PreservedOffsetAnnotations)
BC.MIB->setOffset(*Item.first, Item.second);
for (auto [Instr, Label] : PreservedLabelAnnotations)
BC.MIB->setLabel(*Instr, Label);
}

// Check for dirty state in MCSymbol objects that might be a consequence
Expand Down
7 changes: 6 additions & 1 deletion bolt/lib/Passes/FixRISCVCallsPass.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,12 @@ void FixRISCVCallsPass::runOnFunction(BinaryFunction &BF) {

MCInst OldCall = *NextII;
auto L = BC.scopeLock();
MIB->createCall(*II, Target, Ctx);

if (MIB->isTailCall(*NextII))
MIB->createTailCall(*II, Target, Ctx);
else
MIB->createCall(*II, Target, Ctx);

MIB->moveAnnotations(std::move(OldCall), *II);

// The original offset was set on the jalr of the auipc+jalr pair. Since
Expand Down
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