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Documentation preview: https://vllm--62385.org.readthedocs.build/en/62385/ |
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Signed-off-by: Tony Lin <tony.lin@intel.com>
Signed-off-by: Tony Lin <tony.lin@intel.com>
This was referenced Oct 19, 2026
Signed-off-by: Tony Lin <tony.lin@intel.com>
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This pull request has merge conflicts that must be resolved before it can be |
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Design doc: https://github.com/hlin99/vllm/blob/ww43_PR_TPSP_Transformers_1/2/docs/design/tpsp_design.md
Verified model list
Performance
Delivers up to a ~25% boost in E2E TTFT under optimal conditions, subject to individual device compute and communication bottlenecks.
Profiles
#1 PCIE Communication Topology (Communicationas the Long Pole vs. GEMM)
By splitting a slow All-Reduce into fast peer-to-peer (P2P) intra-node copies, we successfully mitigated the All-Reduce bottleneck and overlapped GEMM computations within the communication phase (except for the first and last micro-chunks). This resulted in a ~40% performance gain, as demonstrated in the down_proj + norm example below.
Figure#1.A. TPSP off
Figure#1.B. TPSP on
#2 NVLink Communication Topology (GEMM as the Long Pole vs. Communication)
By tuning SM allocation and chunk size, we successfully split All-Reduce and normalization into Reduce-Scatter + All-Gather + Normalization (RS + AG + Norm), allowing them to overlap seamlessly with GEMM computations(except for the first & last micro chunk). This resulted in a ~8% performance gain, as demonstrated in the down_proj + norm example below.
Figure#2.A. TPSP off
Figure#2.B. TPSP on